• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.275-280
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• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.13-23
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• 2001

This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.46-54
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• 2002

The world was opened by communication network because of fast improvement and diffusion of information communication. And information was effected in important factor that control economy improvement of the country. The country should improve the information security system because of necessity to maintain its information security independently. Therefore we have used the SEED cipher algorithm and designed the cipher chip of the voice band signal using the Xilinx Co. XCV300PQ240 chip. At the result we designed the voice signal cipher chip of the maximum frequency 47.895MHz and the total equivalent gate 27,285.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.687-690
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• 2015

Forward collision warning systems(FCWS) and lane change assist systems(LCAS) need regions of interest for detecting lanes and objects as road regions. Watershed segmentation is effective algorithm that classify the road. That algorithm is split results appear differently depending on Watershed line with local minimum in the early part of the seed. If not road regions or vehicles combined the road's seed, It segment road with the others. For compensate the that defect, It has to adaptive change by road environment. The method is that image segmentate the several of regions of interest. Then It is set in a straight line that is detected in regions of interest. If It was detected cars on seed, seed is adjusted the location. And If It wasn't include the line, seed is adjusted the length for final decision the seed. We can detect the road region using the final seed that selected according to the road environment.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.199-206
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• 2010

Society of digital information becomes gradually advancement, and it is a situation offered various service, but it is exposed to a serious security threat by a fast development of communication such as the internet and a network. There is required a research of technical encryption to protect more safely important information. And we require research for application of security technology in environment or a field to be based on a characteristics of market of an information security. The symmetric key cipher algorithm has same encryption key and decryption key. It is categorized to Block and Stream cipher algorithm according to conversion ways. This study inspects safety and reliability of proposed SEED, Stream cipher algorithm. And it confirms possibility of application on the communication environments. This can contribute to transact information safely by application of suitable cipher algorithm along various communication environmental conditions.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.43-45
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• 2001

본 논문에서는 한국정보보호 진흥원예서 표준으로 개발한 128비트 블록암호 알고리즘의 표준인 SEED를 하드웨어 칩으로 설계 연구하였다. 설계 연구 방법은 기존 암호 연산부의 속도 개선의 한 방법으로 암호 블록의 16 라운드 각각을 하나의 프로세서로 보고, 이를 파이프라인 방식으로 설계하여 암호 연산의 속도를 증진시키는 방법으로 설계하였다. Cadence의 NCVHDL로 Functional Simulation하고, Synopsys의 Compiler II로 Optimize된 Schematic을 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1937-1940
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• 2003

정보보호 평가는 크게 시스템 평가인 CC(Common Criteria)평가와 암호모듈 평가인 CMVP(Cryptographic Module Validation Program)평가로 나눌 수 있다. 본 논문은 국내 표준 암호 알고리즘 SEED를 북미의 CMVP의 3가지 블록 알고리즘 시험방법인 KAT(Known Answer Test), MCT(Monte C미개 Test), MMT(Multi-block Message Test)를 JAVA환경에 적용하여 시범 구현하였다. 테스트 방법으로 CMVP의 MOVS, TMOVS, AESAVS를 선정하여 FIPS 표준을 적용하였다. 구현 환경으로는 JCE기반의 Cryptix를 채택하여 CMVP의 블록 암호 알고리즘 테스트 시스템 중 일부를 구현하였다.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.