• Journal of Astronomy and Space Sciences
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• v.33 no.3
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• pp.229-236
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• 2016

We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary metal-oxide-semiconductor (CMOS) technology). We compare our radiation tolerance data for LPDDR SDRAM with those of general DDR SDRAM. The data confirms that our devices under test (DUTs) are potential candidates for space flight applications.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.415-420
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• 2010

Cryptographic keys for security should be generated by true random number generators that apply irreversible hashing algorithms to initial values taken from a random source. As DRAM shows randomness in its access latency, it can be used as a random source. However, systems with synchronous DRAM (SDRAM) do not easily expose such randomness resulting in highly clustered random numbers. We resolved this problem by using the xor instruction. Statistical testing shows that the generated random bits have the quality comparable to true random bit sequences. The performance of bit generation is at the order of 100 Kbits/sec. Since the proposed random number generation requires neither external devices nor any special circuits, this method may be used in any computing device that employs DRAM.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.753-756
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• 1999

In this research we designed and synthesized an effective Synchronous DRAM controller for Interleaved Column Mode Access with VHDL. When target device was ALTERA CPLD MA$\times$712 105 logic cells were used. The result of the simulation at 66MHz clock operation, the clock-to-output time t$_{co}$ was 4.5㎱ and the SDRAM controller was in good working order.r. good working order.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.765-768
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• 2004

본 논문에서는 2차원 동영상을 SDRAM을 이용하여 실시간 3 차원 입체영상으로 변환하는 장치를 설계 및 구현하였다. 2차원 동영상에서 운동시차를 추출하여 서로 다른 원근 깊이를 갖는 입체영상을 실시간으로 생성하여 기존의 실시간 입체영상 변환기에서 물체의 운동방향과 속도에 제한은 받는 단점을 개선하였다. 본 논문에서는 깊이의 지각요인을 소개하고 기존 실시간 변환방법과 제안한 입체영상 변환 방법의 원리에 대해 설명하였다. 그리고 실시간 영상 처리를 위해 설계한 SDRAM 컨트롤러와 구현한 변환기의 성능을 기술한다.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1104-1110
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.253-259
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• 2018

Recently, small satellite industries are rapidly changing. Demand for high performance small satellites is increasing with the expansion of Earth Observation Satellite market. A next-generation small satellites require a higher resolution image storage capacity than before. However, there is a problem that the HW configuration of the existing small satellite image storage device could not meet these requirements. The conventional data storing system uses SDRAM to store image data taken from satellites. When SDRAM is used in small satellite platform of a next generation, there is a problem that the cost of physical space is eight times higher and satellite price is two times higher than NAND Flash. Using the same satellite hardware configuration for next-generation satellites will increase the satellite volume to meet hardware requirements. Additional cost is required for structural design, environmental testing, and satellite launch due to increasing volume. Therefore, in order to construct a low-cost, high-efficiency system. This paper shows a next-generation solid state recorder unit (SSRU) using MRAM and NAND Flash instead of SDRAM. As a result of this research, next generation small satellite retain a storage size and weight and improves the data storage space by 15 times and the storage speed by 4.5 times compare to conventional design. Also reduced energy consumption by 96% compared to SDRAM based storage devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.60-60
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• 2003

과학위성 1호에는 원자외선 분광기를 포함한 다섯 개의 탑재체가 있다. MMS(Mass Memory System)는 이들 탑재체가 수집한 데이터를 대용량 메모리에 저장한 후 지상국으로 보내는 역할을 하며 우주방사선에 의한 메모리 데이터의 오류와 무선 채널을 통한 Downlink 상에서 발생하는 오류를 최소화하기 위해서 소프트웨어적으로 에러를 정정할 수 있는 Reed-Solomon Code를 사용 하였다. 탑재체의 데이터를 저장하기 위한 대용량 메모리는 총 2Gbits로써 8M SRAM, 64M SDRAM, 256M SDRAM의 세 가지로 구성되어 있으며 메모리 여러 개를 하나의 모듈로 만들고 이 모듈이 층으로 쌓여서 MMS에 탑재되어 있다. SRAM에 비해서 집적도가 매우 높은 SDRAM은 공간을 적게 차지하는 장점은 있지만 우주용이 아니므로 그 안정성을 보장할 수 없으므로 우리별 3호에서 성능이 입증된 SRAM과 같이 탑재되었다. 본 연구에서는 MMS의 구조, 동작모드, Spec 및 연구 개발 내용을 소개한다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.351-355
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• 1999

The amount of data stored, processed and transmitted in the multi-media systems has been growing very fast, especially for the image data. For example, it takes 0.75Mbytes to store 512 12 pixels of 24-bit color image. A video signal with 30 frames per second will require 22.5Mbytes of storage space. To solve this problem, we need a good image compression technique. Recently, many researches on the image compression technique based on the wavelet transform are being pursued to overcome the problems of traditional JPEG. This paper describes the architecture and design of two-dimensional wavelet transform circuit. To keep the sire of the circuit small, we tried to minimize the internal storage space by using external SDRAM. This circuit was designed in Verilog-HDL, synthesized using Design Compiler and verified using Verilog-XL.