Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of SDRAM Controller in HDL

HDL을 이용한 SDRAM Controller의 설계

  • 김용국 (단국대학교 전자컴퓨터공학부) ;
  • 오경욱 (단국대학교 전자컴퓨터공학부) ;
  • 이영희 (단국대학교 전자컴퓨터공학부)
  • Published : 1999.06.01
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Abstract

In this research we designed and synthesized an effective Synchronous DRAM controller for Interleaved Column Mode Access with VHDL. When target device was ALTERA CPLD MA$\times$712 105 logic cells were used. The result of the simulation at 66MHz clock operation, the clock-to-output time t$_{co}$ was 4.5㎱ and the SDRAM controller was in good working order.r. good working order.

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