• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.239-245
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• 2016

Deramping technique has been widely used to acquire high resolution SAR(Synthetic Aperture Radar) images for the advantage of the data size and the processing time. However, unwanted spurious signals caused by SAR hardware can be leaked in the process of converting into a digital signal through the ADC(Analog-Digital Converter) and added in a echo signal. These tones make image quality degrade significantly. In order to solve this problem, the unwanted tones need to be detected by analysing the characteristic of the noise tone and then effectively removed from raw data. In this paper, we propose a method for efficiently removing noise tone on the raw data based on the characteristic of spurious signals.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.352-353
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• 2013

본 연구에서는 12bit 1MSps 연속 근사화 아날로그-디지털 변환기(Analog to Digital Converter : ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 0.18um 1Metal 6Poly CMOS 공정을 이용하였고, Cadence tool을 이용하여 시뮬레이션 및 레이아웃 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 6mW였고, 입력 신호의 주파수가 100kHz 일 때, SNDR은 69.53dB, 유효 비트수는 11.26bit의 결과를 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.371-374
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• 2013

In this paper, a sensor node circuit using solar energy harvesting is proposed. PMU(Power Management Unit) manages the energy converted from a solar cell. In order to supply a constant voltage to the sensor node, an LDO (Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter). The circuit has been designed in 0.35um CMOS process.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.130-137
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• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.365-367
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• 2013

본 논문에서는 $0.18{\mu}m$ CMOS 공정 기술을 이용하여 12-bit 1MSps 연속 근사화 아날로그-디지털 변환기(Analog to Digital Converter : ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 진행하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 5.5mW였고, 입력 신호의 주파수가 100kHz일 때, SNDR은 70.03dB, 유효 비트수는 11.34bit의 결과를 보였다. 설계된 변환기는 $0.8mm{\times}0.7mm$ 크기로 레이아웃 되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.861-862
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• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.