• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.472-472
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• 2000

An analog signal conditioner using fuzzy logic technique, which has multiple-input and multiple-output terminals, is proposed in this paper. The proposed signal conditioner can be employed to linearly translate the level of signals to a standard voltage signal (1-5V) and convert the form of signals to a standard current signal (4-20mA). The implementation method based on the use of a commercial 8-bit microcontroller, the analog-to-digital (A/D) converters, the digital-to-analog (D/A) converters and the voltage-to-current (V/I) converter. The simulation result and the experimental results are presented, which further confirm the feasibility of this approach.

• Journal of Korean Institute of Industrial Engineers
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• v.40 no.3
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• pp.342-357
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• 2014

The present study analyzes the relationship between research and development (R&D) inputs and performance of a national technology innovation R&D program using successive binary Logistic regression models based on a typical R&D logic model. In particular, this study focuses on to answer the following three main questions; (1) "To what extent, do the R&D inputs have an effect on the performance creation?"; (2) "Is an obvious relationship verified between the immediate predecessor and its successor performance?"; and (3) "Is there a difference in the performance creation between R&D government subsidy recipient types and between R&D collaboration types?" Methodologically, binary Logistic regression models are established successively considering the "Success-Failure" binary data characteristic regarding the performance creation. An empirical analysis is presented analyzing the sample n = 2,178 R&D projects completed. This study's major findings are as follows. First, the R&D inputs have a statistically significant relationship only with the short-term, technical output, "Patent Registration." Second, strong dependencies are identified between the immediate predecessor and its successor performance. Third, the success probability of the performance creation is statistically significantly different between the R&D types aforementioned. Specifically, compared with "Large Company", "Small and Medium-Sized Enterprise (SMS)" shows a greater success probability of "Sales" and "New Employment." Meanwhile, "R&D Collaboration" achieves a larger success probability of "Patent Registration" and "Sales."

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.467-474
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• 1990

In this paper, the circuit that has characteristics of high speed and low dissipation is described. A 4:1 parallel ADC is constructed by using the designed SCFL(Source Coupled FET Logic). The results of simulation shows that comparators is obtained integrated nonlinearity, $\pm$28mV, compared with limiting value, $\pm$68mV, at 66NHz input signal and 2Gs/s Niquist rates and this paper describes low power dissipation about 0.43W by reducing the elements in a ADC design.

• ETRI Journal
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• v.28 no.5
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• pp.574-582
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• 2006

In this paper, a new error concealment algorithm is proposed for the H.264 standard. The algorithm consists of two processes. The first process uses a fuzzy logic method to select the size type of lost blocks. The motion vector of a lost block is calculated from the current frame, if the motion vectors of the neighboring blocks surrounding the lost block are discontinuous. Otherwise, the size type of the lost block can be determined from the preceding frame. The second process is an error concealment algorithm via a proposed adapted multiple-reference-frames selection for finding the lost motion vector. The adapted multiple-reference-frames selection is based on the motion estimation analysis of H.264 coding so that the number of searched frames can be reduced. Therefore the most accurate mode of the lost block can be determined with much less computation time in the selection of the lost motion vector. Experimental results show that the proposed algorithm achieves from 0.5 to 4.52 dB improvement when compared to the method in VM 9.0.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.4
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• pp.437-446
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• 2018

This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{\mu}s$ with a vector of length 48 with 2 non-zero elements.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Structural Engineering and Mechanics
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• v.27 no.1
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• pp.77-97
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• 2007

When assessing buildings that may collapse during a large earthquake, conventional rapid visual screening procedures generally provide good results when identifying buildings for further investigation. Unfortunately, their accuracy at identify buildings at risk is not so good. In addition, there appears to be little room for improvement. This paper investigates an alternative screening procedure based on fuzzy logic and artificial neural networks. Two databases of buildings damaged during the Athens earthquake of 1999 are used for training purposes. Extremely good results are obtained from one database and not so good results are obtained from the second database. This finding illustrates the importance of specifically collecting data tailored to the requirements of the fuzzy logic based rapid visual screening procedure. In general, results demonstrate that the trained fuzzy logic based rapid visual screening procedure represents a marked improvement when identifying buildings at risk. In particular, when smaller percentages of the buildings with high damage scores are extracted for further investigation, the proposed fuzzy screening procedure becomes more efficient. This paper shows that the proposed procedure has a significant optimisation potential, is worth pursuing and, to this end, a strategy that outlines the future development of the fuzzy logic based rapid visual screening procedure is proposed.

• Proceedings of the Korean Society for Bio-Environment Control Conference
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• 2005.05a
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• pp.207-213
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• 2005

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.863-868
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• 1992

This paper presents a method on applying Genetic Algorithm(GA), which is a well-known high performance optimizing algorithm, to construct the self-organizing fuzzy logic controller. Fuzzy logic controller considered in this paper utilizes Sugeno's hybrid inference method, which has an advantage of simple defuzzification process in the inference engine. Genetic algorithm is used to find the optimal parameters in the FLC. The proposed approach will be demonstrated using 2 d.o.f robot manipulator to verify its effectiveness.