• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2002년도 추계학술대회논문집
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• pp.881-885
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• 2002

This paper presents the performance and the algorithm of a 1/3-octave band spectrum control system. The system is developed to provide various spectrums in a high intensity acoustic chamber. The required spectrum, which usually comes from launch vehicle company, starts from 25Hz band and ends 10kHz band. Automatic spectrum control system is preferred since the system requires short settling time to guarantee the safety of test objects and to reduce the amount of operating gas. The developed system adapted a PCI data-acquisition/signal-generation board installed in a personal computer to implement whole control logic. The control software used three cascade digital Butterworth filters using software. The filers are designed following ANSI S1.11 standard to implement 1/3 octave band filter bank. The graphical user interface of the system guides the user to follow standard operation procedure. The averaged control spectrum showed less than 0.05 dB in every running 1/3-octave band.

• 유공압시스템학회논문집
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• 제7권2호
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• pp.7-12
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• 2010

In these days, the researches about hybrid and fuel cell electric vehicles are actively performed due to the environmental contamination and resource exhaust. Specially, the technology of regenerative braking, converting heat energy to electric energy, is one of the most effective technologies to improve fuel economy. This paper developed a regenerative braking control algorithm that is considered vehicle stability. The vehicle has a inline motor at front drive shaft and has a EHB(Electo-hydraulic Brake) system. The control logic and regenerative braking control algorithm are analyzed by MATLAB/Simulink. The vehicle model is carried out by CarSim and the driving simulation is performed by using co-simulation of CarSim and MATLAB/Simulink. From the simulation results, a regenerative braking control algorithm is verified to improve the vehicle stability as well as fuel economy.

• International Journal of Precision Engineering and Manufacturing
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• 제3권1호
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• pp.66-75
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• 2002

The crane operation used fur transporting heavy loads causes a swinging motion with the loads due to the crane\`s acceleration and deceleration. This sway causes the suspension ropes to leave their grooves and can cause serious damage. Ideally, the purpose of a crane system is to transport loads to a goal position as soon as possible without any oscillation of the rope. Currently, cranes are generally operated based on expert knowledge alone, accordingly, the development of a satisfactory control method that can efficiently suppress object sway during transport is essential. The dynamic behavior of a crane shows nonlinear characteristics. When the length of the rope is changed, a crane becomes a time-varying system thus the design of an anti-sway controller is very difficult. In this paper, a nonlinear dynamic model is derived for an industrial overhead crane whose girder, trolley, and hoister move simultaneously. Furthermore, a fuzzy logic controller, based on expert experiments during acceleration, constant velocity, deceleration, and stop position periods is proposed to suppress the swing motion and control the position of the crane. Computer simulation is then used to test the performance of the fuzzy controller with the nonlinear crane model.

• Journal of Advanced Marine Engineering and Technology
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• 제21권4호
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• pp.393-403
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• 1997

In this paper, we proposed an optimal identification method of identifying the membership func¬tions and the fuzzy rules for the stabilization controller of the nonlinear system by RVEGA( Real Variable Elitist Genetic Algo rithm l. Although fuzzy logic controllers have been successfully applied to industrial plants, most of them have been relied heavily on expert's empirical knowl¬edge. So it is very difficult to determine the linguistic state space partitions and parameters of the membership functions and to extract the control rules. Most of conventional approaches have the drastic defects of trapping to a local minima. However, the proposed RVEGA which is similiar to the processes of natural evolution can optimize simulta¬neously the fuzzy rules and the parameters of membership functions. The validity of the RVEGA - based fuzzy controller was proved through applications to the stabi¬lization problems of an inverted pendulum system with highly nonlinear dynamics. The proposed RVEGA - based fuzzy controller has a swing -. up control mode(swing - up controller) and a stabi¬lization one(stabilization controller), moves a pendulum in an initial stable equilibrium point and a cart in an arbitrary position, to an unstable equilibrium point and a center of the rail. The stabi¬lization controller is composed of a hierarchical fuzzy inference structure; that is, the lower level inference for the virtual equilibrium point and the higher level one for position control of the cart according to the firstly inferred virtual equilibrium point. The experimental apparatus was imple¬mented by a DT -- 2801 board with AID, D/A converters and a PC - 586 microprocessor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2744-2746
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• 2001

이 논문에서는 이동 로봇을 위하여 퍼지이론과 Dempster-Shafer 이론을 이용한 불확실한 환경에서의 센서기반 네비게이션 방법을 제안한다. 제안된 제어기는 장애물 회피 동작과 목적지 찾기 동작을 위한 2개의 행동 모듈로 구성되어 있다. 2개의 행동 모듈은 각각 퍼지 이론으로 학습되었고, 적절한 행동 선택 방법으로 선택되게끔 하였다. 견고한 퍼지 제어기를 가진 로봇이 실험 환경내에서 안전하게 움직이기 위하여 자동으로 지도를 구축(Map Building) 하도록 하였다. 이 실험에서 구성된 맵은 평면상의 격자를 중심으로 작성되었고 로봇의 센서에서 읽어들인 센서 값은 D-S 추론 이론을 이용하여 기존의 맵과 혼합되어진다. 즉, 로봇이 움직일때 마다 실험 환경내에서 새로운 정보를 읽어 들이고, 그 정보로 인하여 기존의 지도가 새로운 지도로 갱신되는 것이다. 이러한 작업을 거치면서 로봇은 장애물과 충돌없이 배회하는 것 뿐 아니라 설정된 목적지까지도 쉽게 찾아갈 수가 있다. 실험에 대한 안정성과 확신을 검증 받기 위하여 실제 로봇에 적용하기보다는 먼저 이동 로봇의 시뮬레이션으로 실험 해 보고자 한다.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2008년 영문 학술대회
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• pp.84-88
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• 2008

The UAV propulsion system that will be operated for long time at more than 40,000ft altitude should have not only fuel flow minimization but also high reliability and durability. If this UAV propulsion system may have faults, it is not easy to recover the system from the abnormal, and hence an accurate diagnostic technology must be needed to keep the operational reliability. For this purpose, the development of the health monitoring system which can monitor remotely the engine condition should be required. In this study, a fuzzy trend monitoring method for detecting the engine faults including mechanical faults was proposed through analyzing performance trends of measurement data. The trend monitoring is an engine conditioning method which can find engine faults by monitoring important measuring parameters such as fuel flow, exhaust gas temperatures, rotational speeds, vibration and etc. Using engine condition database as an input to be generated by linear regression analysis of real engine instrument data, an application of the fuzzy logic in diagnostics estimated the cause of fault in each component. According to study results, it was confirmed that the proposed trend monitoring method can improve reliability and durability of the propulsion system for a long endurance UAV to be operated at medium altitude.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 한국산학기술학회논문지
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• 제18권7호
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• pp.102-108
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• 2017

기존 기술과 신기술의 확산 및 대체 과정에서 발생하는 기술적 불연속성 현상은 단일 기술 및 복수 기술의 확산 및 대체 현상의 거동을 이해하는데 중요하다. 본 연구에서는 기술적 불연속성 구간의 개념에 대해 정의하고, 이 구간을 측정할 수 있는 정량적 지표들에 대한 측정 모형을 개발하였다. 문헌리뷰 및 모형 도출을 바탕으로 기술적 불연속성 구간에 대해 정의 및 측정 모형을 제시하였고, 도출한 모형의 정합성을 반도체 산업의 기술대체 사례를 바탕으로 검증하였다. 기술적 불연속성 구간은 기존 기술과 신기술의 S곡선이 시간에 따라 동시에 존재하면서, 기존 기술의 성능이 신기술의 성능보다 높은 구간으로 정의된다. 또한 기술적 불연속 구간은 불연속 시간 및 불연속 성능으로 측정가능하며, 불연속 시간 및 불연속 성능지표는 불연속 구간에서의 기존 기술과 신기술의 시간 차이 및 성능 차이로 모형화 된다. 본 연구는 기술적 불연속성 현상에 대한 이해뿐만 아니라 기술 확산 및 대체 현상의 전체적인 거동의 이해에 유용할 것이다.

• 전자공학회논문지
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• 제52권9호
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• pp.63-73
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• 2015

본 논문에서는 특별한 보정기법 없이 채널 간 오프셋 부정합 문제를 최소화한 2채널 time-interleaved (T-I) 구조의 10비트 120MS/s 파이프라인 SAR ADC를 제안한다. 제안하는 ADC는 4비트-7비트 기반의 2단 파이프라인 구조 및 2채널 T-I 구조를 동시에 적용하여 전력소모를 최소화하면서 빠른 변환속도를 구현하였다. 채널 간에 비교기 및 잔류전압 증폭기 등 아날로그 회로를 공유함으로써 일반적인 T-I 구조에서 선형성을 제한하는 채널 간 오프셋 부정합 문제를 추가적인 보정기법 없이 최소화할 뿐만 아니라 전력소모 및 면적을 감소시켰다. 고속 동작을 위해 SAR 로직에는 범용 D 플립플롭 대신 TSPC D 플립플롭을 사용하여 SAR 로직에서의 지연시간을 최소화하면서 사용되는 트랜지스터의 수도 절반 수준으로 줄임으로써 전력소모 및 면적을 최소화하였다. 한편 제안하는 ADC는 기준전압 구동회로를 3가지로 분리하여, 4비트 및 7비트 기반의 SAR 동작, 잔류전압 증폭 등 서로 다른 스위칭 동작으로 인해 발생하는 기준전압 간섭 및 채널 간 이득 부정합 문제를 최소화하였다. 시제품 ADC는 고속 SAR 동작을 위한 높은 주파수의 클록을 온-칩 클록 생성회로를 통해 생성하였으며, 외부에서 duty cycle을 조절할 수 있도록 설계하였다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 10비트 해상도에서 각각 최대 0.69LSB, 0.77LSB이며, 120MS/s 동작속도에서 동적 성능은 최대 50.9dB의 SNDR 및 59.7dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 $0.36mm^2$이며, 1.1V 전원전압에서 8.8mW의 전력을 소모한다.

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.25-33
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• 2011

본 논문에서는 CIS 응용을 위해 제한된 폭을 가지는 10비트 50MS/s 0.13um CMOS 3단 파이프라인 ADC를 제안한다. 통상 CIS에 사용되는 아날로그 회로에서는 수용 가능한 조도 범위를 충분히 확보하기 위해 높은 전원전압을 사용하여 넓은 범위의 아날로그 신호를 처리한다. 그 반면, 디지털 회로에서는 전력 효율성을 위해 낮은 전원전압을 사용하므로 제안하는 ADC는 해당 전원전압들을 모두 사용하여 넓은 범위의 아날로그 신호를 낮은 전압 기반의 디지털 데이터로 변환하도록 설계하였다. 또한 2개의 잔류 증폭기에 적용한 증폭기 공유기법은 각 단의 증폭동작에 따라 전류를 조절함으로써 증폭기의 성능을 최적화 하여 전력 효율을 더욱 향상시켰다. 동일한 구조를 가진 3개의 FLASH ADC에서는 인터폴레이션 기법을 통해 비교기의 입력 단 개수를 절반으로 줄였으며, 프리앰프를 제거하여 래치만으로 비교기를 구성하였다. 또한 래치에 입력 단과 출력 단을 분리하는 풀-다운 스위치를 사용하여 킥-백 잡음으로 인한 문제를 최소화하였다. 기준전류 및 전압회로에서는 온-칩 저 전력 전압구동회로만으로 요구되는 정착시간 성능을 확보하였으며, 디지털 교정회로에는 신호특성에 따른 두 종류의 레벨-쉬프트 회로를 두어 낮은 전압의 디지털 데이터가 출력되도록 설계하였다. 제안하는 시제품 ADC는 0.35um thick-gate-oxide 트랜지스터를 지원하는 0.13um CMOS로 제작되었으며, 측정된 DNL 및 INL은 10비트에서 각각 최대 0.42LSB, 1.19LSB 수준을 보이며, 동적 성능은 50MS/s 동작속도에서 55.4dB의 SNDR과 68.7dB의 SFDR을 보인다. 시제품 ADC의 칩 면적은 0.53$mm^2$이며, 2.0V의 아날로그 전압, 2.8V 및 1.2V 등 두 종류의 디지털 전원전압에서 총 15.6mW의 전력을 소모한다.