• The Journal of the Korea Contents Association
• /
• v.7 no.2
• /
• pp.92-99
• /
• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.3
• /
• pp.345-353
• /
• 2011

An 1.485 Gbit/s video signal transmission system using the carrier frequency of H-band(220~325 GHz) was implemented and demonstrated for the first in domestic. The RF front-end was composed of Schottky barrier diode sub-harmonic mixers(SHM) and frequency triplers, and diagonal horn antennas for transmitter and receiver, respectively. The transmitted carrier frequency of 246 GHz was implemented in the H-band, and LO frequencies of H-band SHM is 120 GHz and 126 GHz for transmit and receive chains, respectively. The modulation scheme is ASK(Amplitude Shift Keying) where IF frequency is 5.94 GHz and the envelop detection was used in heterodyne receiver architecture, and direct detection receiver using ZBD(Zero Bias Detector) was implemented as well. The 1.485 Gbit/s video signal with HD-SDI format was successfully transmitted over wireless link distance of 5 m and displayed on HDTV at the transmitted average output power of 20 ${\mu}W$.

• The KIPS Transactions:PartA
• /
• v.15A no.1
• /
• pp.1-8
• /
• 2008

An occlusion culling method, one of visibility culling methods, excludes invisible objects or triangles which are covered by other objects. As it reduces computation quantity, occlusion culling is an effective method to handle complex scenes in real-time. But an existing common occlusion culling method, such as hardware occlusion query method, sends objects' data twice to GPU and this causes processing overheads once for occlusion culling test and the other is for rendering. And another existing hardware occlusion culling method, VCBP, can test objects' visibility quickly, but it neither test bounding volume nor return test result to application stage. In this paper, we propose a single pass occlusion culling method which uses temporal and spatial coherency, with effective occlusion culling hardware architecture. In our approach, the hardware performs occlusion culling test rapidly with cache on the rasterization stage where triangles are transformed into fragments. At the same time, hardware sends each primitive's visibility information to application stage. As a result, the application stage reduces data transmission quantity by excluding covered objects using the visibility information on previous frame and hierarchical spatial tree. Our proposed method improved maximum 44%, minimum 14% compared with S&W method based on hardware occlusion query. And the performance is increased 25% and 17% respectively, compared to maximum and minimum performance of CHC method which is based on occlusion culling method.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.3
• /
• pp.18-27
• /
• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.533-536
• /
• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.399-402
• /
• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Smart Structures and Systems
• /
• v.20 no.3
• /
• pp.263-272
• /
• 2017

This paper presents the time response of a mixed vibration system with the viscous damping and the hysteretic damping. There are two ways to derive the time response of such a vibration system. One is an analytical method, using the contour integral of complex functions to compute the inverse Fourier transforms. The other is an approximate method in which the analytic functions derived by Hilbert transform are expressed in the state space representation, and only the effective eigenvalues are used to efficiently compute the transient response. The unit impulse responses of the two methods are compared and the change in the damping properties which depend on the viscous and hysteretic damping values is investigated. The results showed that the damping properties of a mixed damping vibration system do not present themselves as a linear combination of damping properties.

• Proceedings of the KSRS Conference
• /
• 2003.11a
• /
• pp.849-851
• /
• 2003

A location-based service or LBS in a cellular telephone network is a service provided to the subscriber based on his current geographic location. This position can be known by user entry or a GPS receiver that he carries with him, but most often the term implies the use of a function built into the cell network that uses the known geographic coordinates of the base stations through which the communication takes place. One implication is that knowledge of the coordinates is owned and controlled by the network operator, and not by the end user. Location utility service provides two kinds of functions, geocoder and reverse geocoder. Geocoder converts an address into a coordinate and reverse geocoder changes a coordinate into an address. Because location utility service is the first step to progress LBS, various servises such as directory, routing, presentation, and etc require to access that. In this paper, we will describe the architecture of LBS platform and the concept and the role of location utility service.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.44 no.1
• /
• pp.46-56
• /
• 2008

A numerical model analysis was performed to analyze the motion and mooring tension response of submersible fish cage systems in irregular waves and currents. Two systems were examined: a submersible cage mooring with a single, high tension mooring and the same system, but with an additional three point mooring. Using a Morison equation type model, simulations of the systems were conducted with the cage at the surface and submerged. Irregular waves(JONSWAP spectrum) with and without a co-linear current with a magnitude of 0.5m/s were simulated into the model as input parameters. Surge, heave and pitch dynamic calculations were made, along with tension responses in the mooring lines. Results were analyzed in both the time and frequency domains and linear transfer functions were calculated.

• Journal of Korean Institute of Industrial Engineers
• /
• v.22 no.2
• /
• pp.255-263
• /
• 1996

Optical fiber systems play an essential role In today's telecommunications networks. The recently standardized SONET technology has made a ring structure the preferred architecture for inter-city communication networks. In designing a SONET with ring structure, we consider inserting optional cites, which are not necessary in constructing the SONET, but cost-effective in connecting essential nodes in the ring. This problem is modeled as Steiner ring problem. Efficient heuristic procedures are developed based on the procedures for the traveling salesman problem. Computational results show that the proposed algorithm is excellent compared to the optimal solution. The error bound by the proposed method is 2 - 6% in experimented problems.