• Journal of Mechanical Science and Technology
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• v.19 no.2
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• pp.634-648
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• 2005

Performed here is a comparative assessment study for the probabilistic fracture mechanics approach of the pressurized thermal shock of the reactor pressure vessel. A round robin consisting of one prerequisite deterministic study and five cases for probabilistic approaches is proposed, and all organizations interested are invited. The problems are solved by the participants and their results are compared to issue some recommendation of best practices and to assure an understanding of the key parameters in this type of approach, like transient description and frequency, material properties, defect type and distribution, fracture mechanics methodology etc., which will be useful in the justification through a probabilistic approach for the case of a plant over-passing the screening criteria. Six participants from 3 organizations responded to the problem and their results are compiled and analyzed in this study.

• Journal of KIISE:Information Networking
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• v.32 no.3
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• pp.359-369
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• 2005

Delay estimation is a difficult Problem in computer networks. Accurate one-way delay estimation is crucial because it serves a very important role in network performance and thus application design. RTT(Round Trip Time) is often used as an approximation of the delay, but because it is a sum of the forward and reverse delays, the actual one-way delay cannot be estimated accurately from RTT. To estimate one-way delay accurately, this paper proposes a new scheme that analytically derives one-way delay, forward and reverse delay respectively. We show that the performance of TCP can improve dramatically in asymmetric networks using our scheme. A key contribution of this paper is that our one-way deiay estimation is much more accurate than RTT estimation so that TCP can quickly find the network capacity in the slow start phase. Since RTT is the sum of the forward and reverse delays, our scheme can be applied to any protocol that is based on RTT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.109-116
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• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.85-94
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• 2010

Many RFID systems use dynamic slotted ALOHA to identify the label information of the RFID tags. One of the key problems in the RFID system is how to estimate the number of RFID tags up to the desired level of accuracy. In this paper, we present the framework of tag estimation algorithm for the collision-oblivious (CO) reader which can only decide whether the tag response is successful or not. Thus, the CO reader must rely on the success estimator to predict the RFID tag population. We propose two estimation algorithms to predict the number of RFID tags, named the memoryless success estimator (MSE) and the intersection-based success estimator (ISE). The MSE considers only the estimate obtained at the current inventory round, while the ISE finds an appropriate intersection interval of the existing estimates collected at every inventory round. Through the simulation results, we demonstrate that the ISE is a fast, accurate, and controllable estimator whose performance is close to that of the collision/idle estimators.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.177-185
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• 2000

In this paper CPLD design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then each subround is executed using one clock. To improve clock frequency, online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. The cryptographic coprocessor is designed using Altera EPF10K100GC503-3 CPLD device and its operation is verified by encryption or decryption of text files through ISA bus interface. It consists of about 29,300 gates and performance of CPLD chip is about 44 Mbps encryption or decryption rate under 18 Mhz clock frequency and ECB mode.

• Research in Community and Public Health Nursing
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• v.30 no.3
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• pp.295-306
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• 2019

Purpose: There has been a growing recognition that person-centered care enhances the quality of life of nursing home residents with dementia. This study was conducted to develop a person-centered dementia care online education program for direct care staff in long-term care facilities. Methods: Delphi method with expert group was used to validate contents. We developed 61 draft items based on literature review. Twenty experts participated in consecutive three round surveys including 5-point Likert scale questions and open-ended questions. Based on experts' opinions, the content validity ratio for content validity and the coefficient of variation for stability were calculated. Results: Three-round Delphi surveys and additional feedback from the expert panel established a consensus of core contents: 1) dementia (7 categories), 2) person-centered care (6 categories), 3) communication (8 categories), and 4) behavioral and psychological symptoms of dementia (6 categories). Specific sub-categories in each category were differentiated according to the job qualifications (65 sub-categories for registered nurses, 64 sub-categories for nursing aids, and 41 sub-categories for personal care workers). Conclusion: This delphi study identified person-centered dementia education curricula, in which the person-centered approach should be a key policy priority in Korean long-term care system. Now it is urgently needed to develop education programs utilizing online platforms that enable efficient and continuous learning for long-term care staff, which can contribute to behavior changes in the person-centered dementia care approach and improvement of care quality in long-term care facilities.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.42 no.3
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• pp.61-69
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• 2019

The concept of carsharing involves sharing a small number of reserved cars to be used individually by a larger number of people as required. This study examines the operating parameters of one-way carsharing systems in order to determine the appropriate operating conditions that minimizes the lost sales rate. Five operating parameters are tested in this study: the number of stations, the average number of vehicles per station, the rate of one-way trip, the average number of staffs per station, and the relocation policy. The performance of round-trip carsharing systems is also compared to that of one-way carsharing systems. A simulation model is developed and simulations are performed to determine the appropriate combination of operating parameter and levels. The simulation results show that the average number of vehicles per station is the most critical parameter. Other key findings obtained from this research are as follows. First, applying the appropriate relocation policy to one-way carsharing systems can allow more customers to rent vehicles than the traditional round-trip carsharing systems. Second, the appropriate relocation policy should be selected based on the average number of vehicles per station in order to minimize the lost sales rate. Third, the number of stations does not affect the lost sales rate. This study findings will provide tools to understand impact of the carsharing system parameters on the efficiency of the carsharing operations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.175-182
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• 2023

Differential cryptanalysis is one of the analysis techniques for block ciphers, and uses the property that the output difference with respect to the input difference exists with a high probability. If random data and differential data can be distinguished, data complexity for differential cryptanalysis can be reduced. For this, many studies on deep learning-based neural distinguisher have been conducted. In this paper, a deep learning-based neural distinguisher for PIPO 64/128 is proposed. As a result of experiments with various input differences, the 3-round neural distinguisher for the differential characteristics for 0, 1, 3, and 5-rounds achieved accuracies of 0.71, 0.64, 0.62, and 0.64, respectively. This work allows distinguishing attacks for up to 8 rounds when used with the classical distinguisher. Therefore, scalability was achieved by finding a distinguisher that could handle the differential of each round. To improve performance, we plan to apply various neural network structures to construct an optimal neural network, and implement a neural distinguisher that can use related key differential or process multiple input differences simultaneously.

• Educational Technology International
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• v.20 no.1
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• pp.25-55
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• 2019

The core purpose of the study is to develop and validate an ADDIE model based instructional model for English Language Teaching (ELT) in early childhood classroom in Bangladesh as an aid to teachers to reconstruct their knowledge and experience more strategically, and for them to design and implement their instruction more structurally. This study is developmental in nature which has been divided in five phases as follows. Phase I: Existing methods and instructional strategy review, Phase II: Instructional model development, Phase III: Delphi 1st round, Phase IV: Delphi 2nd round and Phase V: Model validation. After reviewing relevant literature and existing strategy in phase I, the 1st version of instructional model is made phase II. Next in phase III and phase IV, two rounds of Delphi have been conducted where experts related to different concerning areas of this study reviewed the 1st version and gradually the final version of the instructional model is made. Finally, the instructional model for English teachers of early childhood classroom in Bangladesh got validated by the same Delphi panelists in Phase V. In respect with each phases of ADDIE, the instructional model elaborates the 1) representative key points, 2) instructors' activities prescribed for the instructors, 3) supporting strategies. Both the conceptual and procedural models are included in this study for clearer identification of the whole process. Lastly the study provides some recommendations for instructors and practitioners on choosing the instructional model like doing prior need analysis, incorporating teacher training programs, training students, keeping on researching for finding effective teaching technique and tools and being open to changes etc. In addition, the study also acknowledges its limitations like not being able to consider the psychological factors due to time limitation. Finally, at the end the study points out the areas that welcome further research.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.