• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7B
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• pp.653-663
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• 2002

UMTS/GPRS has its own QoS architecture, but additionally needs to support IP-QoS to provide Internet services. This paper describes an IP-QoS provisioning mechanism in the MPLS-based UMTS/GPRS network. We propose a QoS framework that includes the functional architecture of the MPLS-based GPRS networks and the efficient scheduling mechanism based on Diffserv model. The proposed scheduling mechanims is especially focused on the QoS support for real-time services. It also includes a new buffer management scheme that combines the priority queuing and weighted round robin method. The ns-2 simulator has been used to verify the validity of the proposed scheduling method.

• Journal of the Korean Society for Marine Environment & Energy
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• v.9 no.2
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• pp.92-97
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• 2006

Hull forms of a high speed small boat have been developed through numerical studies. A round bilge type hull form has been drived form a using chine hull form with HCAD, a hull form variation software. Wave resistance and the flow fields around the ships have been computed using well-known software, WAVIS. This software employs Rankine source method with non-linear tree surface condition as well as dry transom boundary conditions. The round bilge hull form showed better resistance performance than to the chine hull form for the whole speed range. However, considering the building and labor costs of the small shipyard, the chine hull form has been selected and its wave resistance characteristics has been improved by modifying the bow regions and applying the stem wedge. It is found that the effect of stem wedge is quite satisfactory to improve the resistance characteristics of high speed chine hull form.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1653-1658
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. In this study, we compare the characteristics of various arbitration policies using TLM(Transaction Level Model) method. Fixed priority, round-robin, TDMA and Lottery bus policies are used in general arbitration method. We analyze the merit and demerit of these arbitration policies.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1259-1262
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• 2004

Detecting environmental hazards and monitoring remote terrain are among many sensor network applications. In case of fire detection, it is significantly valuable to monitor fire-spot's shape and trend in time. Mobile ad hoc sensor nodes right round are responsible for sensoring, processing and networking packets, or even launching extinguisher. In this paper, we proposed a ring-oriented Multicast architecture based on "Fisheye State Routing" (MFSR) to organize a group of mobile ad hoc sensor nodes in a multicast way. It is familiar with traditional mesh-based multicast protocol [1] in mobile ad hoc network, trying to concentrates on efficiency and robustness simultaneously. Certain applications-based solution for hazards is proposed, quantitative results including architecture and recovery algorithms of MFSR are also investigated in this paper.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.6
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• pp.365-371
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• 2003

Input queued switch is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queued. The input queued switch, however, suffers the HOL-Blocking, which limits its throughput to 58%. To overcome HOL-Blocking problem, many input-queued switch controlled by a scheduling algorithm. Most scheduling algorithms are implemented based on a centralized scheduler which restrict the design of the switch architecture. In this paper, we propose a simple scheduler called Pipelined Round Robin (PRR) which is intrinsically distributed by each input port. We presents to show the effectiveness of the proposed scheduler.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.144-147
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• 2000

Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.9
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• pp.4156-4162
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• 2013

This study was peformed to determine optimum induction heating conditions for a round bar of crankshaft. Four induction heating conditions were proposed and evaluated, employing numerical method, based on electromagnetic and sequential heat transfer analyses, resulting in optimum induction heating conditions which are finally proposed based on peak temperatures at heating zone and minimum temperature gradient through thickness of a round bar after 1 hour induction heating.

• Journal of the Korea Society of Computer and Information
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• v.24 no.4
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• pp.1-9
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• 2019

LRR(Loose Round Robin) warp scheduling policy for GPU architecture results in high warp-level parallelism and balanced loads across multiple warps. However, traditional LRR policy makes multiple warps execute long latency operations at the same time. In cases that no more warps to be issued under long latency, the throughput of GPUs may be degraded significantly. In this paper, we propose a new warp scheduling policy which utilizes latency hiding, leading to more utilized memory resources in high performance GPUs. The proposed warp scheduler prioritizes memory instruction based on GTO(Greedy Then Oldest) policy in order to provide reduced memory stalls. When no warps can execute memory instruction any more, the warp scheduler selects a warp for computation instruction by round robin manner. Furthermore, our proposed technique achieves high performance by using additional information about recently committed warps. According to our experimental results, our proposed technique improves GPU performance by 12.7% and 5.6% over LRR and GTO on average, respectively.