• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.125-128
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• 2002

This paper designed a cipher process, which used SEED-Algorithm that is totally domestic technique. This cipher processor is implemented by using SEED-cipher-Algorithm and pipeline scheduling architecture. The cipher is 16-round Feistel architecture but we show just 16-round Feistel architecture for brevity in this thesis. Of course, we can get the result of the 16-round processing by addition of control part simply. Furthermore, it has pipelined architecture, so the speed of cipher process is the faster than others when we performed a cipher a lot of data. The schedule-function can performed the two-cipher process simultaneously, such as using two-cipher processors.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.347-350
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• 2002

In the input buffer switch system, VOQ(Virtual Output Queue) archives 100% throughput. The VOQ with the systolic architecture maintains an uniform performance regardless of a number of Packet class and output port, so that it doesn't have a limitation of scalability. In spite of these advantages, the systolic architecture VOQ is difficult to change sorting order In this paper, we Proposed a systolic architecture VOQ which support weighted round robin(WRR) algorithm to provide with flow control service.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2261-2266
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of Ocean Engineering and Technology
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• v.24 no.4
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• pp.59-65
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• 2010

This study presents the design procedure for optimizing the semi-planing hull form, including appendages, using numerical and experimental methods. Four different referenced semi-planing hull forms were compared to determine their hydrodynamic performances, and one of the hull forms was modified for optimum operation at high-speed conditions (0.4 < $F_{NL}$ < 0.9). The optimized, semi-planing hull form was tested in the towing tank to investigate its resistance characteristics. Also, the results of the model tests with differing design parameters were used to choose the stern wedge and the spray strip to improve the hydrodynamic performance at high speeds.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1879-1884
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• 2013

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Structural Engineering and Mechanics
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• v.52 no.5
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• pp.889-901
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• 2014

Very long life fatigue tests were carried out on 16Mn steel base metal and its welded joint by using the ultrasonic fatigue testing technique. Specimen shapes (round and plate) were considered for both the base metal and welded joint. The results show that the specimens present different S-N curve characteristics in the region of $10^5-10^9$ cycles. The round specimens showed continuously decreasing tendency while plate specimens showed a steep decreasing step and an asymptotic horizontal one. The fatigue strength of round specimen was found higher than plate specimen. The fatigue strength of as-welded joint was 45.0% of the base material for butt joint and 40% for cruciform as-welded joint. It was found that fracture can still occur in butt joint beyond $5{\times}10^6$ cycles. The cruciform joint has a fatigue limit in the very long life fatigue regime ($10^7-10^9$ cycles). Fatigue strength of butt as-welded joint was much higher as compared to cruciform as-welded joint. Improvement in fatigue strength of welded joint was found due to UPT. The observation of fracture surface showed crack mainly initiated from welded toe at fusion areas or geometric discontinuity sites at the surface in butt joint and from welded toe in cruciform joint.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of the Korean Institute of Landscape Architecture International Edition
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• no.2
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• pp.140-146
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• 2004

All-round development of urban greenery network morphology is an integrated part of urban space system. The greenbelt construction of the Middle Ring Line is capable of changing linear planning and merging the peripheral greenery construction with 3-D space design to jointly form a broad open space.

• Journal of KIISE:Information Networking
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• v.28 no.4
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• pp.631-640
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• 2001

Round robin scheduling discipline, which is a sort of frame-based scheduling, is quite simple and straightforward for handling multiple queues, and by putting a different weight on each queue, a network can offer differentiated services such as different bandwidth, or delay bound. The most typical algorithm among this disciplines is the weighted round robin(WRR). Also, WRR algorithm can be implemented efficiently by dynamic binary scheduling wheel(DBSW) architecture. This paper performs the analysis of the DBSW architecture and compares the results with simulation results. The analysis data and simulation data show that the DBSW structure decreases average buffer length because it is capable of maintaining the allocated weight of each VC correctly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.50-56
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.