• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.33-37
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• 2011

In this study, the degradation mechanism of mounted chip resistors with Ag-epoxy isotropic conductive adhesives (ICAs) under the humidity exposure ($85^{\circ}C$/85%RH) was examined by electrical resistance change and microstructural study. The effect of the chloride content in Ag-epoxy ICA on joint stability was also examined. The increasing range of the electrical resistance in the typical ICA joint was greater than that in the low Cl content ICA joint. In the case of the typical ICA joint, Sn oxides such as SnO, $SnO_2$, and Sn-Cl-O were formed inhomogeneously on the surface of the Sn plating during the $85^{\circ}C$/85%RH test. In contrast, no Sn-Cl-O was found in the low Cl content ICA joint during the $85^{\circ}C$/85%RH. It is suggested that Cl in Ag-epoxy ICA accelerate the electrical degradation of Sn plated chip components joined with Ag-epoxy ICA.

• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.49-57
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• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05e
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• pp.23-26
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• 2003

The flat transformer, typically, has a number of parallel single turn secondary windings. Each secondary winding is coupled to the same primary winding. Therefore, the current in each secondary winding is equal to the ampere-turns in the primary winding, and to each other. These characteristics are particularly advantageous where parallel rectifiers are used. The windings share the current equally, with no need for ballast resistors or other added components. In this study, the ferrite magnetic core samples of Mn-Zn system for the Flat transformer are manufactured and the electrical and magnetic characteristics of its tested. The density of sample FO2-2 sintered at $1350^{\circ}C$ is $4.00kg/m^3$, which shows the good microstructural state. The initial permeability and saturation flux density of FO2 at room temperature is 2700 and 510mT, individually. The power loss of FO2 samples at 250kHz have been ranged $350kW/m^3$ to $80kW/m^3$ with temperature. And the minimum power loss of sample FO2-2 showed at $70^{\circ}C$, which property seems very positive to apply for a flat transformer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.634-638
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• 2015

Phase currents should be measured in real time for vector control of a 2-phase induction motor. Generally, the phase currents of the motor are measured using two Hall current sensors installed at the output terminal of an inverter. Unfortunately, Hall current sensors are expensive and uneconomical because a vector-controlled inverter for 2-phase induction motor is mainly used in low-power and low-price applications. This paper proposes a low-cost current measurement method using two shunt resistors instead of expensive Hall current sensors. The proposed method can measure the phase currents under all operating conditions of the motor. This method was applied to an experimental vector-controlled inverter for 2-phase induction motor of 220[V]/360[W] and was verified through computer simulations and experimentation.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.113.1-113.1
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• 2011

PEMS (printed electro-mechanical system) is fabricated by means of various printing technologies. Passive and active compo-nents in 2D or 3D such as conducting lines, resistors, capacitors, inductors and TFT(Thin Film Transistor), which are printed withfunctional materials, can be classified in this category. And the issue of PEMS is applied to a R2R process in the manu-facturing process. In many electro-devices, the vacuum process is used as the manufacturing process. However, the vacuum process has a problem, it is difficult to apply to a continuous process such as a R2R(roll to roll) printing process. In this paper, we propose an ESD (electro static deposition) printing process has been used to apply an organic solar cell of thin film forming. ESD is a method of liquid atomization by electrical forces, an electrostatic atomizer sprays micro-drops from the solution injected into the capillary with electrostatic force generated by electric potential of about several tens kV. ESD method is usable in the thin film coating process of organic materials and continuous process as a R2R manufacturing process. Therefore, we experiment the thin films forming of PEDOT:PSS layer and active layer which consist of the P3HT:PCBM. The organic solar cell based on a P3HT/PCBM active layer and a PEDOT:PSS electron blocking layer prepared from ESD method shows solar-to-electrical conversion efficiency of 1.42% at AM 1.5G 1sun light illumination, while 1.86% efficiency is observed when the ESD deposition of P3HT/PCBM is performed on a spin-coated PEDOT:PSS layer.

• Journal of Advanced Navigation Technology
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• v.19 no.3
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• pp.224-229
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• 2015

In this paper, we derived the design equation and implemented the unequal Gysel power divider that is one external resistors using the ABCD parameters analysis. Conventional unequal Gysel divider is difficult to obtain the characteristics of isolation and return loss at between output ports because it can't select a theoretical value of external resistor. To solve those problems, we design the new unequal Gysel power divider with transmission lines and one external resistor that has the characteristics of conventional unequal Gysel divider. To validate this design method, we simulated and measured an 4: 1 unequal Gysel power divider at the center frequency 1 GHz. The measured performances agreed well with the simulation results.

• Journal of the Korea Computer Industry Society
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• v.2 no.3
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• pp.363-368
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• 2001

This paper introduced cascading technique as a new technology composed of two pulse transformers and presented the experimental data and results. To obtain the stable pulse voltage adopted cascading technique, we designed and tested a compact pulse generator by adjusting the load resistors and input voltage. Adopting cascading technique to load, we found that average cascading voltage was about 62$\%$ of theoretical value. Cascading ratio was calculated at almost 19 compared with non cascading voltage.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.1-7
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• 2005

The effect of trimming process to adjust accurate resistance of a thin-film resistor was studied with respect to low temperature coefficient of resistance(TCR) and high precision. The characteristics of a thin-film resistor fabricated by sputtering were investigated depending on trimming condition and annealing temperature. Measured results showed that the characteristic of a thin-film resistor was degraded with increased trimming speed. However, an average resistance deviation and a TCR were improved to $0.26\%$ and 52.77[ppm/K], respectively, through annealing treatment. Also, thin-film resistors with 1 k$\Omega$ and 10k$\Omega$ showed better performance compared to a resistor with 100k$\Omega$. The Optimal trimming speed and annealing temperature were 20mm/sec and 539K, respectively, and under this optimal condition, a thin-film resistor with an average resistance deviation of $0.31\%$ and a TCR of below 10[ppm/K] was obtained.

• Journal of The Korean Association For Science Education
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• v.24 no.3
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• pp.612-620
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• 2004

The purpose of this study was to investigate how middle and high school students represent circuit diagrams with different shapes but electrically same. What prototypes of circuit which students possessed were, how students represented the connection of resistors, and what criteria used while grouping the circuit diagrams were investigated. The participants were 10 middle and 10 high school students. The results show that they represented the circuit diagrams by the geometrical resistor configurations rather than physics principles, not considering the presence of a junction or a battery on the branch. This representation was constrained by the circuit prototypes. Middle and High school students seems to have the own way of representing circuit diagrams without considering physics principles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.