• The korean journal of orthodontics
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• v.18 no.1 s.25
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• pp.189-207
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• 1988

In almost all biologic systems, mechanically induced electric charge separation is a fundamental phenomenon. Since the hypothesis was established that the generation of electric potentials in bone by mechanical stress including muscular force might control the activity in bone by mechanical stress including muscular force might control the activity of osseous cells and their biopolymeric byproduct, the concept of electrically mediate growth mechanism, which involves biological growth and bone remodeling by any means, in living systems has been applied clinically and experimentally to orthopedic fracture repair, the regulation of orthodontic tooth movement, epiphyseal cartilage regeneration, etc. On the other hand, recent numerous research data available show apparently that the mandibular condyle has the characteristics of growth center as well as growth site. In addition, there exists a considerable difference of opinion as to the role of external pterygoid muscle in condylar growth. In view of these evidences, this. experiment was performed to investigate the effect of the galavic current on the growth of the mandible and condyle for elucidating the nature of condylar growth. The bimetallic device was composed of silver and platinum electrode connected with resistor (3.9 Mohm), which was expected to produce galvanic current of 23.6 nA according to the galvanic principle. The 25 Sprague-Dawley rats were divided into two group, 2 week group comprising 8 animals exposed to satanic current for 2 weeks and 3 control animals not exposed for 2 weeks, 4 week group comprising 10 animals in experimental group and 4 animals in control group applied for 4 weeks respectively. The experimental rats were subjected to application of the galvanic current invasively to codylar head surface and the control groups with sham electrode. On the basis of anatomic and histologic data from the mandibular condyle of experimental and control group, the following results were obtained. 1. After 2 weeks, there was no increase of mandibular size in experimental group over that of the control group. 2. After 4 weeks, the size of the condylar head was larger in experimental group than that of the control. 3. In 2 week group, the thickness of the mitotic compartment and hypertrophic chondroblastic layer was increased in experimental group. 4. In 4 week group, the number and the size of the hypertrophic chondroblasts were increased significantly on experimental group over that of the control group. 5. The application of the satanic current caused an increase in chondrocytic hypertrophy and intercellular matrix in both groups.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.719-724
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• 2016

This paper describes the performance improvement of an inrush current limiter to prevent damage or malfunctions in power converters due to the inrush current. When the power converter of military radar is operated, the circuit breaker of the power converter is often activated because the overcurrent flows through the circuit breaker of the power converter. Therefore, this study performed a cause analysis of the problem, which is a larger current flow than the intended current(250A). The operation principle of an inrush current limiter and SCR (Silicon Controlled Rectifier) used in the inrush current limiter was analyzed. As a result, the overcurrent flow through the circuit breaker was found to be due to dv/dt triggering of SCR. Based on cause analysis, this paper proposes a technique by adding the resistor in front of the SCR to prevent an unnecessary inrush current. Finally, the effectiveness of the improvement was verified by measuring the output current in the inrush current limiter. The power converter equipped with the improved inrush current limiter operated for more than 1 year without the circuit breaker of the power converter being activated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1899-1909
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• 2007

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

• Journal of Advanced Navigation Technology
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• v.22 no.6
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• pp.642-647
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• 2018

In this paper, an unequal power divider based on adjusting electrical length of uniform transmission line is presented. This divider consists of three uniform transmission lines and one isolation resistor and have the different port impedances of input and output. The feature of proposed divider can changed the power dividing ratio to adjust only electrical length of uniform transmission lines. To verify the feasibility of proposed power divider, two divider circuits are designed, one is 1:2 power dividing ratio divider with $60{\Omega}$ uniform transmission line and $40{\Omega}$ input port impedances and $45{\Omega}$ output port impedances, the performance data were measured the insertion losses of 1.7 dB/ 5.0 dB, return losses of more than -30 dB and isolation of more than -35 dB. The other is 1:4 power dividing ratio divider with $40{\Omega}$ uniform transmission line and $50{\Omega}$ input port impedances and $75{\Omega}$ output port impedances, the performance data were measured the insertion losses of 1.3 dB/ 6.8 dB, return losses of more than -12 dB and isolation of more than -19 dB. The measured performance data agreed well with the simulated results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1409-1415
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• 2021

The Gysel divider has the advantage of easily setting the resistor in the circuit. If the line impedance in the Gysel divider is set differently, the input signal can be distributed to the two output ports at various distribution ratios. This paper proposes the Gysel divider that can change the power distribution to 1:3 or 3:1 by changing the line impedance. The impedance change of the line can be implemented by placing a floating copper plate on the bottom of the microstrip-line. When the floating copper plate and the ground plane are connected, the line operates as the microstrip-line, and when the floating copper plate and the ground plane are disconnected, the line operates as the coplanar-line. The proposed Gysel divider was fabricated at the center frequency of 1.5GHz. The fabricated 3:1 Gysel divider has a stable value S₁₁ of below -17dB, S₂₁/S₃₁ of 4.8±0.2dB, S₂₁(to high output port) of -1.39±0.12dB and S₃₁(to low output port) of -6.15±0.08dB over 1.3~1.7GHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.109-116
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• 2022

In this paper, we propose a band rejection filter (BRF) with a state variable filter (SVF) structure to effectively remove the influence of 60 Hz line frequency noise introduced into the sensor system. The conventional BRF of the SVF structure uses an additional operational amplifier (OPAMP) to add a low pass filter (LPF) output and a high pass filter (HPF) output or an input signal and a band pass filter. Therefore, the notch frequency and the notch depth that determine the signal attenuation of the BRF greatly depend on the tolerance of the resistors used to obtain the sum or difference of the signals. On the other hand, in the proposed BRF, since the BRF output is formed naturally within the SVF structure, there is no need for a combination between each port. The notch frequency of the proposed BRF is 59.99 Hz, and it can be confirmed that it is not affected at all by the tolerance of the resistor through the Monte Carlo simulation results. The notch depth also has an average of -42.54dB and a standard deviation of 0.63dB, confirming that normal operation as a BRF is possible. Also, with the proposed BRF, noise filtering was applied to the electrocardiogram (ECG) signal that interfered with 60 Hz noise, and it was confirmed that the 60 Hz noise was appropriately suppressed.

• Journal of IKEEE
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• v.27 no.1
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• pp.45-52
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• 2023

Cold-junction correction(CJC) and disconnection detection circuit design of various thermocouples(TC) and multi-channel TC interface circuit using them were designed. The CJC and disconnection detection circuit consists of a CJC semiconductor device, an instrumentation amplifier(IA), two resistors and a diode for disconnection detection. Based on the basic circuit, a multi-channel interface circuit was also implemented. The CJC was implemented using compensation semiconductor and IA, and disconnection detection was detected by using two resistor and a diode so that IA input voltage became -0.42V. As a result of the experiment using R-type TC, the error of the designed circuit was reduced from 0.14mV to 3㎶ after CJC in the temperature range of 0℃ to 1400℃. In addition, it was confirmed that the output voltage of IA was saturated from 88mV to -14.2V when TC was disconnected from normal. The output voltage of the designed circuit was 0V to 10V in the temperature range of 0℃ to 1400℃. The results of the 4-channel interface experiment using R-type TC were almost identical to the CJC and disconnection detection results for each channel. The implemented multi-channel interface has a feature that can be applied equally to E, J, K, T, R, and S-type TCs by changing the terminals of CJC semiconductor devices and adjusting the IA gain.