• 한국진공학회:학술대회논문집
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• 한국진공학회 2001년도 제21회 학술발표회 초록집
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• pp.173-173
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• 2001

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.121-122
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• 2000

The understanding of reset scheme is essential for the driving of AC PDP (Plasma Display Panel). The characteristics of reset period of AC PDP was examined with the variation of pulse time and voltage in the ADS (Address Display Separated) driving method presented by Fujitsu,. The addressing characteristics showed drastic change as a function of the erasing time and addressing pulse width. In this paper, these results were explained by the change of wall charge variation, and it was estimated with the currents through each electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.631-634
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• 2005

We propose a new address-while-display (AWD) driving method to obtain a high contrast ratio and a wide driving margin which is composed of a short ramp reset period, a sustain period and an address period as the basic unit. The short ramp reset (SRR) pulse made it possible to assure the wide operating voltage margin and minimize the background luminance by redistributing the wall charges between address and scan electrode. As a result, a high dark room contrast ratio of 10000 to 1 could be obtained with a wide operating voltage margin of 40V for stable address.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.259-262
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• 2005

Image retention is a kind of fatal shortcoming of the AC PDPs for realizing high-quality picture. In this work, the measurement method of image retention was proposed using temporal measurement of luminance, CIEXYZ tristimulus values, IR emission of reset pulse, and temperaturel. On the base of temporal measurement of luminance, CIEXYZ tristimulus value, and IR emission of reset pulse, the retention time of Ne+5%Xe gas-mixture discharge was about 2 hours after white window image. However, it was about 20 minute on the base of temporal measurement of temperature.

• 한국군사과학기술학회지
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• 제9권4호
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• pp.71-80
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• 2006

Strapdown Inertial navigation systems consist of an inertial sensor assembly(ISA), electronic modules to process sensor data, and a navigation computer to calculate attitude, velocity and position. In the ISA, most gryoscopes such as RLGs and FOGs, have digital output, but typical accelerometers use current as an analog output. For a high precision inertial navigation system, sufficient stability and resolution of the accelerometer board converting the analog accelerometer output into digital data needs to be guaranteed. To achieve this precision, the asymmetric error and A/D reset scale error of the accelerometer board must be properly compensated. If the relation between the acceleration error and the errors of boards are exactly known, the compensation and estimation techniques for the errors may be well developed. However, the A/D Reset scale error consists of a pulse-train type term with a period inversely proportional to an input acceleration additional to a proportional term, which makes it difficult to estimate. In this paper, the effects on the acceleration output for auto-pilot situations and the effects of A/D reset scale errors during horizontal alignment are qualitatively analyzed. The result can be applied to the development of the real-time compensation technique for A/D reset scale error and the derivation of the design parameters for accelerometer board.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.719-721
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• 2012

본 시험은 군전자장비의 전원제어부품으로 사용되는 TPS54315소자에 대하여 과도방사선에 따른 과도응답특성인 Upset/Latch-up특성을 평가하기 시험으로 포항가속기 연구소내의 Test LINAC 조사시설을 이용하여 $1.43{\times}10^7$rad(si)/sec~$1.25{\times}10^8$rad(si)/sec 선량률 조건에서의 실측시험을 수행하였다. 시험결과 $1.0{\times}10^8$rad(si)/sec 이후 Latch-up 현상이 확인되었으며 연속펄스 인가 시 Latch-up상태에서 정상상태로 복귀하는 결과를 확인하였다. 또한 이러한 현상은 과도방사선에 의한 광전류가 내부전원 Reset로직을 트리거 시킴으로써 Latch-up상태에서의 전원바이어스를 일시적으로 차단함에 따라 발생된 것으로 본 실험을 통하여 Reset회로가 내장된 소자의 경우 일부 Latch-up현상과 동시에 Reset회로가 트리거 되는 경우 Latch-up상태에서 정상상태로 복귀되는 결과를 확인하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권6호
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• pp.297-301
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• 2006

In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

• 전기학회논문지
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• 제60권5호
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• pp.993-998
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• 2011

In this paper we suggest new criteria for the classification of the electrode gap between common and scan electrodes. The electrode gap is categorized as a short, middle, and long gap according to the criteria. Among these structures, we focus on the erase waveform of a mid-gap structure. we report an unstable discharge arising from the erase ramp period in a mid-gap structure. Based on the Vt close curve, we analyze the unstable discharge at various conditions. Our analysis reveals that the unstable discharge is ignited between surface electrodes and caused by un-erased wall charges accumulated on the outer edges of electrodes. By reducing the voltage level of the last sustain pulse, the problem is solved.

• 조명전기설비학회논문지
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• 제17권2호
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• pp.17-22
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• 2003

본 연구에서는 mP의 ADS 구동방식에서 초기화기간의 프라이밍 방전 특성에 대하여 실험적인 해석을 하였다. 방전에 의해 축적되는 벽전하의 총량과 벽전하가 축적되는 시간은 프라이밍 펄스의 폭과 무관하다. 또한 과잉 벽전하에 의한 자기소거 방전은 프라이밍 방전에 의한 벽전하량과 관계가 있으며 또한 프라이밍 방전에 의해 생성되는 공간전하와도 관계가 있다. 실험결과 프라이밍 펄스 폭은 8[$\mu\textrm{s}$], 전압은 163[V] 정도가 최적이다. 그리고 자기소거방전을 돕는 공간전하는 파라이밍 방전이 발생한 직후로부터 약 16[$\mu\textrm{s}$] 동안 존재한다. 그러므로 효과적인 초기화 과정을 위한 프라이밍 펄스의 폭은 16[$\mu\textrm{s}$] 이내가 적당하다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.11-12
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• 2009

In this paper, we propose a high voltage driver IC(HVIC) for LCD and PDP TV power supply. The proposed circuit is included novel a shoot-through protection and a pulse generation circuit for the high voltage driver IC. The proposed circuit has lower variation of dead time and pulse-width about a variation of a process and a supply voltage than a conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also the proposed pulse generation circuit prevent from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, and its variation is maximum 170 ns(68 %) about a variation of a process and a supply voltage. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD process parameter, and a simulation is carried out using Spectre.