• 한국전기전자재료학회논문지
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• 제28권3호
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• pp.149-153
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• 2015

As the temperature of the panel increases in AC-PDPs, the minimum driving voltage increases. Also, as the more the number of discharge increases in cells, the probability of the strong dark discharge in the reset period increases. In this study, we investigated the relationship between the lag time of the discharge and the mechanism of mis-discharges which are the black noise and bright noise. We conclude that the variation of time lag characterizes the properties of exo-electron emission from MgO. Thus, we found that the main factor of the mis-discharges is the rate of change of the electron emission ability from the MgO surface.

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 1993년도 한국우주과학회보 제2권2호
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• pp.22-22
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• 1993

We developed the low energy electron detector (LEED) for KITSAT-B which was launched on September 26, 1998. The sensor head is mounted on the top of the satellite so that it can measure the precipitating electron flux along the Magnetic field line in the auroral zone at 820 km altitude. The detector system is composed of 4 parts : the electrostatic analyzer, the spira10on detector, the discriminator / Preamplifier, and the interface to the spacecraft. The analyzer limits the access to the spiraltron only to the electrons of certain energies which are determined by the electrostatic field across the two coaxial cylindrical analyzer plates. The energy spectrum of the detector in consideration is about 100 eV to 6.7 KeV, which is swept in 1.6 seconds and divided into 16 bins. It 81so is 1.6 second reset period after each swept, We will discuss the technical features of the system as well as the future observational schedule.

• 전자공학회논문지
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• 제50권3호
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• pp.174-178
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• 2013

플라즈마 디스플레이 패널에서 기입기간 동안 공통전극에서의 벽전하를 이용하여 기입방전특성을 향상시키기 위하여 수정된 구동 파형을 제시한다. 플라즈마 디스플레이의 구동방식에 있어서 초기화 기간 후에 상판의 두 전극에는 음전하가 쌓이게 되고 하판의 기입전극에는 양전하가 쌓이게 된다. 기입기간 중의 기입방전은 주사펄스와 기입펄스가 동시에 인가될 때 발생되는데 주사전극의 음전하와 기입전극의 양전하가 주로 이용된다. 반면에 공통 전극에서는 기입기간 동안 파형인가 없이 전압만 유지하기 때문에 공통전극의 벽전하는 크게 기여하지 않는다. 본 연구에서는 기입기간 중 주사 및 기입 펄스의 인가시각에 맞춰 공통 전극에서도 펄스를 인가하여 기입방전 특성을 조사하였다. 공통 전극에서의 인가전압의 높이와 펄스의 인가시각에 따른 기입 방전특성을 조사하는 실험을 각각 진행하였으며 그 결과 최적의 전압높이와 인가시각 조건하에서 기입방전의 발생시간을 종래보다 약 200 ns 정도 단축시켰다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.179-182
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• 1997

In a training simulator for power plant, operator's action in the MCR(Main Control Room) are given to plant process and computer system model as an inputs, and the same response as in real power plant is provided in real time. Inter-process communication and synchronization are especially important among various inputs. In the plant simulator, to simulate the digital control system such as FOXBORO SPEC-200 Micro control system, modification and adaptation of control card(CCC) and its continuous display station(CDS) is necessary. This paper describes the modeling and simulation of FOXBORO SPEC-200 Micro control system applied to Younggwang nuclear power plant unit #3 & 4, and its integration process to the full-scope replica type training simulator. In a simulator, display station like CDS of FOXBORO SPEC-200 Micro control system is classified as ITI(Intelligent Type Instrument), which has a micro processor inside to process information and the corresponding alphanumeric display, and the stimulation of ITI limits the important functions in a training simulator such as backtrack, replay, freeze and IC reset. Therefore, to achieve the better performance of the simulator, modification of CDS and special firmware is developed to simulate the FOXBORO SPEC-200 Micro control system. Each control function inside control card is modeled and simulated in generic approach to accept the plant data and control parameter conveniently, and debugging algorithms are applied for massive coding developed in short period.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2033-2036
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• 1997

In this paper, we proposed a novel current-fed DC-DC converter with multi-output. It has two winding reactor in series with the input source of the converter. By using the 2nd winding recycling the energy stored in the reactor to the input, the double-outputs DC-DC converter can be created, which makes it a good choice for a multi-output power supply with more outputs and has savings in cost and space. The steady state and dynamic characteristics of the converter are analyzed in detail by using the state space averaging method. It is found that the maximum value of $V_{o2}$ exists in the 2nd output and also during the MOSFET off period, the energy stored in the magnetizing inductance is reset through auxiliary winding $N_3$, so the duty cycle is restricted to 50%. Theoretical and experimental results were taken from the converter rated at switching frequency 50kHz. input voltage 50V. output voltage 5V. 12V and output power 65W. As a result, both results were well consistent. Therefore, it is varified the validity of the proposed converter in this paper.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1189-1192
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• 2007

We propose new driving schemes, asymmetry and long gap mode, of PDP having auxiliary electrode between scan and common electrode. For the asymmetric modes, the auxiliary electrode located nearly center of the primary electrodes is connected to the scan of common electrode during all periods of reset, address and sustain. For the long gap mode, it is electrically disconnected or maintained at dc voltage of Vs/2 during sustain period except the first several sustain pulses. The proposed structure and driving method can provide higher luminous efficacy by minimizing consumption energy. The effectiveness of the new driving schemes has been investigated for various Xe partial pressure conditions.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1588-1590
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• 2001

The voltage controlled ramp waveform(VCR) has recently been used in the reset period prior to addressing for plasma display. However, in this paper, the current controlled ramp waveform(CCR) which may prevent the oscillation of gap voltage cause current growth and decrease the background luminance has been suggested. As a result, in case of CCR method, the contrast ratio was about 14% increased compared with VCR method, whereas the addressing and sustainin discharge characteristics of CCR method were same with those of VCR method.

• 조명전기설비학회논문지
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• 제23권2호
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• pp.45-52
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• 2009

본 연구는 Full-HD급 PDP의 고속 구동 구현을 위한 새로운 구동 방식에 관한 연구이다. 새로운 SPA (self-priming address) 구동 파형은 어드레스 구간에서 지속적인 프라이밍 방전을 유지하여 하전 입자 효과를 이용하여 어드레스 방전 지연 시간을 개선하기 위하여 제안되었다. 본 연구에서는 프라이밍 방전의 기본 특성에 대해 조사하였으며, 안정적인 프라이밍 방전을 유지할 수 있는 초기화 펄스 및 프라이밍 램프 펄스를 도출하였다. 특히, 프라이밍 램프 펄스의 기울기가 0.1[$V/{\mu}s$]의 미약한 프라이밍 방전의 경우에 대해서도 기존 방식의 1.2[${\mu}s$]의 어드레스 방전 지연 시간을 0.8[${\mu}s$]로 획기적으로 개선할 수 있는 것을 확인하였다.

• 전자공학회논문지
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• 제51권2호
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• pp.168-172
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• 2014

교류형 플라즈마 디스플레이에서 유지기간 중에 자기소거 방전을 발생시켜서 휘도효율을 향상시키기 위한 새로운 유지 구동방법이 제안된다. 일반적인 AC PDP에서 하나의 서브필드 시간은 초기화, 기입, 유지기간으로 나누어져 있다. 그 중 유지기간 동안에 2개의 상판 전극인 X와 Y 전극에 교대로 사각 유지파형이 인가되어 화상을 표시하기 위한 유지기간 중의 플라즈마 방전이 연속적으로 발생된다. 그러나 일반적인 구동방법에 있어서 하판의 A전극에는 기입기간에서 종래의 구동방법에서는 셀을 선택할 때만 기입파형이 구동되고 유지기간 중에는 접지 상태로 놓여있으므로 유지 방전에 관여하지 않는다. 본 실험에서는 유지기간 중에 자기소거 방전을 발생시켜 휘도효율을 상승시키기 위하여 유지펄스의 뒷부분에서 음의 펄스를 A전극에 인가하였다. A전극의 음의 펄스는 주 유지방전이 발생된 후 셀 내부의 공간전하들을 벽전하로 전환시켜서 3전극의 전위가 접지 상태가 될 때 재 축적된 벽전하로 인하여 방전을 한번 더 유도시켰다. 그 결과, 유지기간 중 A 전극의 전압 높이에 따른 휘도 효율을 측정하였고 최적의 구동전압을 적용했을 때 휘도효율을 측정한 결과 종래와 비교해서 약 40 % 향상되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.