• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.161-164
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• 2009

This paper presents the ZVZCS(Zero Voltage and Zero-Current-Switching) Three-Level converter using the secondary coupled inductor and auxiliary capacitor. The converter with phase-shift control is proposed to reduce the circulating loss in primary and the voltage stress in secondary side. Using a coupled winding of the output inductor, two auxiliary capacitors are generated to reset the primary current at circulating interval.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1398-1400
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• 2005

In this paper, a modular dc-to-dc converter, in order to apply to the control board of train vehicles, is presented. Forward converter with active-clamp reset circuit and synchronous rectifier(SR) is employed to achieve high efficiency. To reduce the size and height of the converter, low profile magnetic components are used. The design and performance of the modular dc-to-dc converter with experiments on a 50W(5V/10A) prototype for the 60V$\sim$140V input voltage range are presented.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.465-471
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• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of Power Electronics
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• v.7 no.4
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• pp.343-352
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• 2007

This paper proposes a modularized charge equalization converter for hybrid electric vehicle (HEV) lithium-ion battery cells, in which the intra-module and the inter-module equalizer are Implemented. Considering the high voltage HEV battery pack, over approximately 300V, the proposed equalization circuit modularizes the entire $M^*N$ cells; in other words, M modules in the string and N cells in each module. With this modularization, low voltage stress on all the electronic devices, below roughly 64V, can be obtained. In the intra-module equalization, a current-fed DC/DC converter with cell selection switches is employed. By conducting these selection switches, concentrated charging of the specific under charged cells can be performed. On the other hand, the inter-module equalizer makes use of a voltage-fed DC/DC converter for bi-directional equalization. In the proposed circuit, these two converters can share the MOSFET switch so that low cost and small size can be achieved. In addition, the absence of any additional reset circuitry in the inter-module equalizer allows for further size reduction, concurrently conducting the multiple cell selection switches allows for shorter equalization time, and employing the optimal power rating design rule allows fur high power density to be obtained. Experimental results of an implemented prototype show that the proposed equalization scheme has the promised cell balancing performance for the 7Ah HEV lithium-ion battery string while maintaining low voltage stress, low cost, small size, and short equalization time.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.89-98
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• 2010

Isolated boost converter is desirable in the dc/dc converter applications where isolation is required and extremely high step up is needed. Transformer used to step up low input voltage into high output voltage must satisfy the volt-sec balance condition. Conventional isolated boost converter is controlled with conducting intervals overlapping. In this case, there is a problem that control circuit is complicated. In this paper, it is proposed and analyzed the isolated boost converter which set up a reset winding for the volt-sec balance of transformer and can construct the control circuit simple by using a self-driven switch. Finally, the validity of the theoretical analyses for the proposed converter is verified by both simulations and experiments on the 10[W] class isolated boost converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1588-1590
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• 2001

The voltage controlled ramp waveform(VCR) has recently been used in the reset period prior to addressing for plasma display. However, in this paper, the current controlled ramp waveform(CCR) which may prevent the oscillation of gap voltage cause current growth and decrease the background luminance has been suggested. As a result, in case of CCR method, the contrast ratio was about 14% increased compared with VCR method, whereas the addressing and sustainin discharge characteristics of CCR method were same with those of VCR method.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.