• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.400-402
• /
• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.109-112
• /
• 2005

AC PDP의 구동파형은 Reset 구간에서 명암비를 높이고 화질향상을 위해서 전압파형을 서서히 증가시키고 또 감소시키는데, 이 전압파형의 기울기와 크기가 온도와 더불어서 PDP의 화질과 관련이 있다. 그래서 본 논문에서는 Reset 구간에서 Y 전극에 인가하는 램프파형의 setup 및 setdown 구간에서의 기울기와 -Vy전압을 온도에 따라서 가변함으로써, 주위의 온도가 상온에서 저온이나 고온으로 변화하여도 PDP의 화질이 영향을 받지 않고 최상으로 유지하게 하는 온도 적응형 RESET 파형 발생회로를 제 안하였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.8
• /
• pp.1734-1740
• /
• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.38-45
• /
• 2010

A new readout circuit involving a pixel-level reset control was studied for 2-D long wavelength infrared focal plane arrays. The integration time of each pixel can be optimized individually and automatically. Hence, the readout circuit has a wide dynamic range and good signal-to-noise ratio characteristics. The readout circuit was fabricated with a $0.35{\mu}m$ 2-poly 4-metal CMOS process for a $128{\times}128$ long wavelength infrared HgCdTe array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The smart reset control with two-step background suppression improves the signal-to-noise ratio to 87dB and the dynamic range to 95.8dB.

• Proceedings of the KIPE Conference
• /
• 1998.07a
• /
• pp.319-322
• /
• 1998

In this paper we further propose to add a very simple regenerative clamping circuit to SSIPP to reduce the voltage stress and to recycle the energy trapped in the leakage inductance of the isolation transformer, thus eliminating the need for a lossy snubber circuit. In addition, this proposed clamping circuit also provides a mechanism to reset the magnetizing current of the output transformer of SSIPP employing a Forward converter as the output stage. Simulations and experimental results are reported to verify the operation and performance of the SSIPP with regenerative clamping.

• Proceedings of the KIEE Conference
• /
• 1999.11b
• /
• pp.6-8
• /
• 1999

This paper presents a method to analyze a forward converter. A transformer is coupled with the forward converter electric circuit and then the finite element analysis considering a hysteresis phenomenon of magnetic core is carried out when the primary or the reset winding conducts current. The analytical method is used to reduce the computation time when the reset winding circuit of the transformer turns off. As a result, the simulation results show a good agreement with experimental ones.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.2
• /
• pp.87-90
• /
• 2010

A new SRAM pixel circuit with RESET Transistor of a LCOS display module was designed for a pico-projector application. A dual-block PWM method was also proposed to realize the field sequential color system having only one LCOS panel. 0.29 inch LCOS panel in SVGA resolution was fabricated and the proposed dual-block PWM method was tested with it. Discontinuity of brightness curve was caused due to multi-pulses and it was improved by the adoption of proper mapping table. With the proposed SRAM with RESET pixel circuit and dual-block PWM method, the test images were successfully demonstrated.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.27 no.6
• /
• pp.464-470
• /
• 2022

A new type of soft-switching forward converter is proposed in this study. By adding only a few components, the inductor, diode, switch, and capacitor exhibit higher efficiency than the conventional forward converter. Therefore, the switching losses of the proposed forward converter are considerably reduced compared with those of the conventional forward converter. In addition, the reset winding is not used because of the capacitor employed in the auxiliary circuit. The auxiliary capacitor is adopted for zero-current-transition operation and for dissipating magnetization energy. The performance of the proposed forward converter is validated using experimental results from a 60 W, single-output, forward converter prototype, and design guidelines are presented.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.3
• /
• pp.53-59
• /
• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Journal of Sensor Science and Technology
• /
• v.17 no.1
• /
• pp.41-52
• /
• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.