• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.756-759
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• 2003

We measure the spatiotemporal wall charge distributions on sustain and address electrodes during reset period in an ac PDP cell using the longitudinal electro-optic amplitude modulation method. We apply several reset waveforms like as ramp, exponentially growing and high voltage pulse, and compare the wall charge characteristics on address electrode as well as sustain electrodes for each reset waveforms.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.385-388
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• 2003

본 논문에서 제안하는 PFD(Phase Frequency Detector)는 Reset을 줄여 응답 속도의 특성을 향상시키기 위해 기존 회로인 Flip-Flop의 D-Latch circuit를 Memory Cell로 대신한 회로이다. 회로의 특성을 검증하기 위해 HSPICE Tool를 이용 simulation 하였으며 Hynix 0.35um CMOS 공정을 사용하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.220-221
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• 2013

본 논문은 OCV 추정기법을 이용한 전류적산법의 SOC Reset 알고리즘을 제안한다. 제안한 알고리즘은 배터리 상황에 따라 OCV 추정을 위한 휴지시간을 달리 설정한다. 이에 따라 짧은 휴지 시에도 SOC Reset Point를 늘려 전류적산법의 오차를 Reset함으로써 SOC 추정 능력을 향상한다. Li-ion 27 Ah/99.9 Wh 배터리의 충 방전 실험을 통해서 OCV 판별 시간을 도출하여 알고리즘을 구현한다. 전기자동차의 주행 패턴을 모사하여 기존의 전류적산법과 비교 실험을 통해 제안한 알고리즘을 검증한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1636-1639
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• 2002

We proposed the new reset waveform for reducing reset period. The square pulse is applied to the address electrode when the ramp pulse increases before a discharge occurs between sustain electrodes. If the discharge occurs between address electrode and X electrode, the wall charge is reversely accumulated between sustain electrodes compared with the applying voltage before the discharge occurs between sustain electrodes. So the next discharge more weakly occurs between sustain electrodes. If the more weak discharge is obtained, it can make the low background luminance and the high contrast ratio and reduce ramp up time in the ramp reset waveform.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제54권6호
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• pp.269-273
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• 2005

In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be implemented by reducing the address discharge time lag through the priming effect. This paper suggests a new ADR(Address During Reset) driving method which provides priming particles by a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately 100ns reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction of about 29$\%$ in linht emitted during the reset period considerably.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.109-112
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• 2005

AC PDP의 구동파형은 Reset 구간에서 명암비를 높이고 화질향상을 위해서 전압파형을 서서히 증가시키고 또 감소시키는데, 이 전압파형의 기울기와 크기가 온도와 더불어서 PDP의 화질과 관련이 있다. 그래서 본 논문에서는 Reset 구간에서 Y 전극에 인가하는 램프파형의 setup 및 setdown 구간에서의 기울기와 -Vy전압을 온도에 따라서 가변함으로써, 주위의 온도가 상온에서 저온이나 고온으로 변화하여도 PDP의 화질이 영향을 받지 않고 최상으로 유지하게 하는 온도 적응형 RESET 파형 발생회로를 제 안하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1391-1392
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• 2007

A selective reset waveform which can improve the dark room contrast ratio in a large sustain gap structure is suggested in this paper. When conventional selective reset discharge is performed, frequent unexpected misfiring happens because of high Vxb and much quantity of negative wall charge formed on Y electrode during final sustain period. The misfiring between sustain electrode and address electrode can be removed by lowering Vxb value and the misfiring between address electrode and scan electrode can be prevented by applying last sustain pulse of 40us and rectangular pulse of Vscan on Y electrode. When the selective reset waveform has one time reset per 8 subfields, black luminance of 1.55 cd/m2 can be obtained without any misfiring.

• Journal of Power Electronics
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• 제7권4호
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• pp.278-285
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• 2007

Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.

• Journal of Advanced Marine Engineering and Technology
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• 제31권4호
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• pp.410-416
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• 2007

PRAM (Phase change random access memory) is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to change the heater electrode material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of heater electrode material parameters using finite element analysis. From the simulation. the reset current of PRAM cell is reduced from 2.0 mA to 0.72 mA as the electrical conductivity of heater is decreased from $1.0{\times}10^6\;(1/{\Omega}{\cdot}m$) to $1.0{\times}10^4\;(1/{\Omega}{\cdot}m$). As the thermal conductivity of heater is decreased, the reset current is slightly reduced. But the reset current of PRAM cell is not changed as the specific heat of heater is changed.