• Progress in Superconductivity
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• v.9 no.2
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• pp.136-139
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• 2008

InAs semiconductor nanowires can provide a promising platform to integrate superconducting quantum circuit, which exploits tunable supercurrent under the operation of gate voltage. We report temperature and magnetic field dependence of the nanowire superconducting junctions, which is in agreement with the proximity-effect theory of superconductor-normal metal-superconductor weak link. Superconducting coherence length of the InAs nanowire is estimated from the fit and magnetic-field dependence of the critical current and the subgap structure of dI/dV is discussed as well.

• Journal of Engineering Education Research
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• v.19 no.2
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• pp.3-7
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• 2016

A flow control system was designed and fabricated to control the flow rate of liquid through the pipe. This control system was composed of hardwares and software, hardwares as controller, gate valve, orifice meter and data aquisition board and software as National instruments Labview program. Control of flow rate was executed by adjusting the pneumatic valve located at the center of pipe line based on the control signal generated by LabView PID control algorithm, which converts analog signal measured by pressure difference of orifice to digital signal to adjust pneumatic valve. For the controller setup Ziegler-Nichols tuning technique was applied and control performances were investigated for not only the disturbance but also the set point changes. Developed system showed good control performances in flow control enough to use as teaching tool of feedback control theory and practice in university, and also as industrial application.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.533-536
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• 1988

For CMOS, this paper propose a new global routing algorithm in which macrocells and I/O padcells can be treated. Not only predefined feedthrough in base array, but also some polysilicon line which are not assigned as inputs are used to prevent the overflow of nets passing through the row. The signal nets are assigned on their feedthrough by the maze router. By treating macrocells and I/O padcell, the routing from internal to I/O cell can be done automatically and a kind of is constraints in design process can be reduced.

• Electronics and Telecommunications Trends
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• v.8 no.4
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• pp.186-204
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• 1993

주문형 집적 회로를 설계하기 위한 툴은 여러 종류가 상용화되어 있다. 반도체 연구단 주문형반도체개발센터는 이의 설계를 위하여 최근 콤파스 툴을 설치했다. 콤파스툴은 게이트 어레이와 셀 방식의 주문형 집적 회로를 설계하기 위한 툴로서 가장 보편적인 툴 중의 하나이다. 본 고는 게이트 어레이 방식 주문형 집적회로의 설계 과정을 상세하게 보임으로써 시스템 설계자 (주문형 집적회로 사용자) 에게는 시스템 설계시 고려할 사항을, 주문형 집적회로 설계자에게는 주문형 집적회로 설계를 위한 지침을 제공하고자 작성하였다. 그리고 주문형 집적회로의 설계 과정을 보다 명확하고 실질적으로 파악하기 위하여 각 설계 과정을 콤파스 툴과 연관하여 설명한다. 그러나, 콤파스 툴은 설계과정을 설명하기 위한 도구로만 사용했으므로 툴 자체에 대한 설명은 생략했다.

• ETRI Journal
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• v.34 no.2
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• pp.284-287
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• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• ETRI Journal
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• v.33 no.3
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• pp.393-400
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• 2011

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

• Proceedings of the IEEK Conference
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• summer
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• pp.70-73
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• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Carbon letters
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• v.13 no.1
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• pp.17-22
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• 2012

Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.409-412
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• 2007

A lot of research for system-on-panel(SOP) have been done to integrate display systems including data driver, gate driver, timing controller, DC-DC converter, and smart functions such as embedded touch screen, ambient brightness sensing and luminance control, finger printing on the glass. Recently, the cost of an one-chip driver IC with various functions has decreased rapidly, and new mobile display interface technologies have been introduced. So it is necessary to examine the feasibility of SOP for practical mobile applications. In this paper, we will re-examine LTPS technologies for mobile displays in terms of various aspects and discuss the practical limitations on SOP technology and future technology trend of mobile displays.

• Advances in robotics research
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• v.2 no.1
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• pp.99-112
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• 2018

The main contribution of this work is the design of a field programmable gate array (FPGA) based ARX-Laguerre proportional-integral observation (PIO) system for fault detection and identification (FDI) in a multi-input, multi-output (MIMO) nonlinear uncertain dynamical robot manipulators. An ARX-Laguerre method was used in this study to dynamic modeling the robot manipulator in the presence of uncertainty and disturbance. To address the challenges of robustness, fault detection, isolation, and estimation the proposed FPGA-based PI observer was applied to the ARX-Laguerre robot model. The effectiveness and accuracy of FPGA based ARX-Laguerre PIO was tested by first three degrees of the freedom PUMA robot manipulator, yielding 6.3%, 10.73%, and 4.23%, average performance improvement for three types of faults (e.g., actuator fault, sensor faults, and composite fault), respectively.