• 한국전기전자재료학회논문지
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• 제29권5호
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• pp.263-267
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• 2016

In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.

• ETRI Journal
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• 제38권4호
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• 예술인문사회 융합 멀티미디어 논문지
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• 제7권3호
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• pp.301-310
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• 2017

양자점 셀룰라 오토마타(QCA: quantum-dot cellular automata)는 나노 크기의 셀을 이용하여 다양한 연산을 수행하며, 매우 빠른 연산속도와 적은 전력손실로 차세대 기술로 떠오르고 있다. 본 논문에서는 QCA 상에서 새로운 유니버셜 게이트(universal gate)를 제안한다. 또한, 유니버셜 게이트를 이용하여 시공간 효율성 측면에서 우수한 XOR 게이트를 제안한다. 유니버셜 게이트는 자기 자신으로 모든 기본 논리 게이트를 만들어 낼 수 있는 게이트이다. 한편, 제안된 유니버셜 게이트는 기본 셀과 회전된 셀을 활용하여 설계한다. 제안된 유니버셜 게이트의 회전된 셀은 3-입력 다수결게이트 구조의 중앙부에 위치한다. 3-입력 다수결 게이트를 이용하여 XOR 게이트를 설계할 때는 5개 이상의 3-입력 다수결 게이트가 사용되지만, 본 논문에서는 3개의 유니버셜 게이트를 사용하여 XOR 게이트를 제안한다. 제안하는 XOR 게이트는 기존의 XOR 게이트보다 사용된 게이트 수가 줄었으며 설계 면적이나 소요 클럭면에서 우수함을 확인할 수 있다.

• Macromolecular Research
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• 제17권9호
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• pp.646-650
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• 2009

We report the fabrication of pentacene organic field-effect transistors (OFETs) using a fluorinated styrene-alt-maleic anhydride copolymer gate dielectric, which was prepared from styrene derivatives with a fluorinated side chain [$-CH_2-O-(CH_2)_2-(CF_2)_5CF_3$] and maleic anhydride through a solution polymerization technique. The fluorinated side chain was used to impart hydrophobicity to the surface of the gate dielectric and maleic anhydride was employed to improve its wetting properties. A field-effect mobility of 0.12 cm$^2$/Vs was obtained from the as-prepared top-contact pentacene FETs. Since various functional groups can be introduced into the copolymer due to the nature of maleic anhydride, its physical properties can be manipulated easily. Using this type of copolymer, the performance of organic FETs can be enhanced through optimization of the interfacial properties between the gate dielectric and organic semiconductor.

• 한국재료학회지
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• 제13권11호
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• 대한토목학회논문집
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• 제26권3D호
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• pp.367-374
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• 2006

본 연구에서는 국내 철도건널목의 지장물 검지 시스템 및 차단제어 시스템의 운영현황을 살펴봄으로써 기존 시스템의 문제점을 보완할 수 있는 새로운 건널목 제어시스템 및 알고리즘을 제시한다. 국내 건널목 제어시스템의 경우 차량 및 지장물 검지를 통해 단순 입구측 및 출구측을 제어하는 방식으로서 도로 교통과는 연계를 하지 못하고 있는 실정이다. 또한 검지시스템과 차단시스템의 신호연계체계의 미비로 인하여 비효율적이며 안전성이 결여된 건널목 운영을 보이고 있다. 본 연구에서는 보다 효율적인 건널목 운영을 위하여 지자계 검지센서와 레이저 검지센서를 통합한 철도 건널목 지장물 진입위반차량 검지시스템과 4분할차단기 알고리즘을 제시하였고, 현장시험을 통하여 본 연구에서 제시한 알고리즘의 신뢰성을 검증하였다. 그 결과 본 연구에서 개발되어진 시스템들은 철도 건널목 제어기기들간의 상호연계가 가능하며, 동시에 차량운전자의 운행 형태를 고려한 차단제어 방식으로 열차와의 충돌사고를 예방할 수 있으리라 기대되어진다.

• 한국조경학회지
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• 제33권2호
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• pp.92-99
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• 2005

The main gate of a university is a element of landscape which improves the quality of campus as well as demarcates the boundary and publicizes the image of university. Therefore, each university strives to differentiate its main gate from that of other universities with a unique form. This research investigates the signs and symbols shown at the university's main gate of 18 universities in Korea, and also presents useful design tips with the objective of bearing the spirit of the campus and its founding ideology. The results of this research as follows: Icons of Sign for 18 universities can be classified into five separate categories: things, human, animal, character, and metaphor. Examples of the 'things' icons include a pen nib, the sun, the cross, a big bell, and so on. Also, the meaning of the represented symbols can be grouped in three separate categories: university's development, contribution to society, and mining of knowledge. From the three category, university development symbol is the most likely to be used.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1992년도 춘계학술발표회
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• pp.84-85
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• 1992

• 한국재료학회:학술대회논문집
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• 한국재료학회 1996년도 재료학회 춘계학술발표회
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• pp.75-75
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• 1996