• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• The Journal of Asian Finance, Economics and Business
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• v.7 no.11
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• pp.13-22
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• 2020

This research explores the appropriate rubber pricing model and the consistent empirical evidence. This model has been derived from the utility function and firm profit-maximization model of commodity goods. The finding shows that the period t - 1 affects expected commodity price and expected profit of commodity production. In fact, a change in the world price of rubber in the past period led to a change in the expected price of rubber in the short run which influenced the expected rubber profit. As a result, the past-period free on board price has an entirety effect on expected farm price of rubber given an exchange rate. In addition, the rubber pricing model indicates that the profit of local farmer on rubber plant depends solely on the world price of rubber in the short run in case of Thailand. In an empirical study, it was found that a change in the price of ribbed smoke sheet 3 in Singapore Commodity Exchange significantly and positively determined the fluctuation of rubber price at the farm gate in Thailand which was consistent with the behavior of the Thai farmers. Both prices are also cointegrated in the long run. That is, the result states that the VECM is an appropriated pricing model for forecasting the farm price in Thailand.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Journal of architectural history
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• v.7 no.2 s.15
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• pp.63-76
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• 1998

Seowon(書院) was an institute for education and sacrificial rite, established privately in rural villages throughout the middle period of the Chosun dynasty(1392-1910), where scholars researched classic studies, cultivated personal characters in accordance with the Neo-Confucianism, nurtured young disciples, and performed rites at a secluded shrine where spiritual tablets of honorees were housed. This study examines the architectural characteristics of Pilamseowon(筆巖書院) in Chans'seong, Chollanamdo Province, Korea. Through the study, the architectural characteristics of Pilamseowon were found as follows: First, Pilamseowon moved twice since it had been established. Second, through the moving, the area of Pilamseowon was expanded and buildings were added. Third, some buildings of Pilamseowon reflect the previous condition of the seowon site. Take Hwakyeonroo(廓然樓) as an example, which is the main entrance pavilion of Pilamseowon. Pavilion is an appropriate type of building in sloped site. Before Hwakyeonroo was moved to the present site, it was located on sloped site, where Hwakyeonroo accordingly took the pavilion type of building. Present site condition of Pilamseowon is plane, nonetheless, Hwakyeonroo has the pavilion type of building, which reflects the previous condition of the building site. Forth, Pilamseowon consists of six spatial domains and each domain has its own entrance gate to outer area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.22 no.8
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• pp.509-514
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• 2010

A numerical simulation of passenger evacuation in a subway station was performed by coupling the passenger flow analysis and the fire simulation. The algorithm of the passenger flow analysis was based on a DEM (Discrete Element Method) using the potential map of the direction vector for each passenger. This algorithm was improved in the present study as to use finer grid smaller than a passenger in order to resolve detailed geometry of the station and to resolve the behavior of passengers in the bottleneck at the ticket gate considering the collision of passengers to a wall or with other passengers. In the fire simulation, the CO distribution predicted by using CFD was used to take into account the effect of toxic gases on the passengers' mobility. The methodology proposed in the present study could be used in designing safer subway station in case of fire occurrence.

• Annual Conference on Human and Language Technology
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• 2016.10a
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• pp.128-133
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• 2016

문장유사도 분석은 문서 평가 자동화에 활용될 수 있는 중요한 기술이다. 최근 순환신경망을 이용한 인코더-디코더 언어 모델이 기계학습 분야에서 괄목할만한 성과를 거두고 있다. 본 논문에서는 한국어 형태 소임베딩 모델과 GRU(Gated Recurrent Unit)기반의 인코더를 제시하고, 이를 이용하여 언어모델을 한국어 위키피디아 말뭉치로부터 학습하고, 한국어 질의응답 시스템에서 질문에 대한 정답을 유추 할 수 있는 증거문장을 찾을 수 있도록 문장유사도를 측정하는 방법을 제시한다. 본 논문에 제시된 형태소임베딩 모델과 GRU 기반의 인코딩 모델을 이용하여 문장유사도 측정에 있어서, 기존 글자임베딩 방법에 비해 개선된 결과를 얻을 수 있었으며, 질의응답 시스템에서도 유용하게 활용될 수 있음을 알 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.20-28
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• 2003

In this paper, we present results of the comparative analysis of the flicker phenomena in the poly-Si TFT-LCD and a-Si:H TFT-LCD arrays for the development and manufacturing of wide-area and high-quality TFT-LCD displays. We used four different types of TFTs; a-Si:H TFT, excimer laser annealed (ELA) poly-Si TFT, silicide mediated crystallization (SMC) poly-Si TFT, and counter-doped lateral body terminal (LBT), poly-Si TFT. We defined the electrical quantity of the flicker so that we could compare the flickers quantitatively for four different 40" UXGA TFT-LCDs. We identify three factors contributing to the flicker, such as charging time, kickback voltage and leakage current, and analyze how much each of three factors give rise to the flincker in the different TFT-LCD arrays. In addition, we suggest and show that, in the case of the poly-Si TFT-LCD arrays, the low-level (minimum) gate voltages should be carefully chosen to minimize the flicker because of their larger leakage currents compared with a-Si TFT-LCD arrays.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.1-6
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• 2008

In this paper, bias control circuit structure have been employed to improve the power added efficiency of the CMOS class-E power amplifier on low input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal. The proposed CMOS class-E power amplifier using bias controlled circuit has been improved the PAE on low output power level. The operating frequency is 2.14GHz and the output power is 22dBm to 25dBm. In addition to, it has been evident that the designed the structure has showed more than a 80% increase in PAE for flatness over all input power level, respectively.