• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.82-88
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• 2014

We study the effect of mesh reordering on Laplacian smoothing for parallel high performance computing systems. Specifically, we use the Reverse-Cuthill McKee algorithm to reorder meshes and use Laplacian Smoothing to improve the mesh quality on Nonuniform memory access architecture-based parallel high performance computing systems. First, we investigate the effect of using mesh reordering on Laplacian smoothing for a single core system and extend the idea to NUMA-based high performance computing systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.1-6
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• 2016

As IPTV has become one of the major Internet services, IPTV users and channels increase rapidly. However, the increased number of channels makes users difficult to find their desired channels. Along with this, the channel switching time of IPTV incurs serious user-perceived delay. To alleviate these problems, this paper presents hybrid schemes that combine channel prefetching and reordering schemes. Simulation experiments show that combining adjacency based prefetching and popular channel reordering reduces the channel seek time by up to 44.7% in comparison with the conventional channel seeking interfaces.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.10
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• pp.4642-4660
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• 2016

One major concern of applying Multipath TCP (MPTCP) to data delivery in heterogeneous wireless networks is that the utilization of asymmetric paths with diverse networking-related parameters may cause severe packet reordering and receive buffer blocking (RB²LOC). Although many efforts are devoting to addressing MPTCP's packet reordering problems, their sender-controlled solutions do not consider balancing overhead between an MPTCP sender and receiver, and their fully MPTCP mode cannot make MPTCP achieve a desired performance. This paper proposes a novel receiver-centric buffer blocking-aware data scheduling strategy for MPTCP (dubbed MPTCP-rec) necessitating the following aims: (1) alleviating MPTCP's packet reordering and RB²LOC problems, (2) improving the MPTCP performance, and (3) balancing load between the MPTCP sender and receiver. Simulation results show that the proposed MPTCP-rec solution outperforms the existing MPTCP solutions in terms of data delivery performance in heterogeneous wireless networks.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.974-983
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• 2005

In genetic algorithms with lotus-based encoding, static gene reordering is to locate the highly related genes closely together. It helps the genetic algorithms to create and preserve the schema of high-quality effectively. In this paper, we propose a static reordering framework for linear locus-based encoding. It differs from existing reorderings in that it is independent of problem-specific knowledge. It makes a complete graph where weights represent the interelationship between each pair of genes. And, it transforms the graph into a unweighted sparse graph by choosing the edges having relatively high weight. It finds a gene reordering by graph search method. Through the wide experiments about several problems, the method proposed in this paper shows significant performance improvement as compared with the genetic algorithm that does not rearrange genes.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.99-106
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• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.26 no.1
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• pp.85-91
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• 2008

When a large sparse matrix is calculated for a horizontal geodetic network adjustment, it needs to go through the process of matrix reordering for the efficiency of time and space. In this study, several reordering methods for sparse matrix were tested, using Sparse Matrix Manipulation System(SMMS) program, total processing time and Fill-in number produced in factorization process were measured and compared. As a result, Minimum Degree(MD) and Mutiple Minimum Degree(MMD), which are based on Minimum Degree are better than Gibbs-Poole-Stockmeyer(GPS) and Reverse Cuthill-Mckee(RCM), which are based on Minimum Bandwidth. However, the method of the best efficiency can be changed dependent on distribution of non-zero elements in a matrix. This finding could be applied to heighten the efficiency of time and storage space for national datum readjustment and other large geodetic network adjustment.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1548-1555
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• 1999

본 논문에서는 하이퍼그래프의 {{{{k분 분할을 위한 서열화(vertex ordering) 알고리즘의 효율을 개선하기 위한 후처리 알고리즘인 재서열법을 소개한다. 제안된 알고리즘은 {{{{k분 분할을 위한 다양한 알고리즘에 쉽게 적용될 수 있다. 보통 초기 분할은 서열화를 기반으로 하는 알고리즘에 의해 형성된다. 그 후 제안된 알고리즘은 클러스터와 정점을 재배열하여 분할하는 과정을 반복함으로써 분할의 효율을 향상시켜간다. 이 방법을 여러 가지 그래프에 적용하여 향상된 결과를 얻었다.Abstract This paper addresses the post-processing algorithm for {{{{k-way hypergraph partitioning by using a cluster and vertex reordering method. The proposed algorithm applies to several {{{{k-way partitioning algorithm. Generally, the initial partition generating method is based on a vertex ordering algorithm. Our reordering algorithm construct an enhanced partitioning by iteratively partition the reodered clusters and vertices. Experimental results on several graphs demonstrate that reodering provides substantial enhancement.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.1043-1048
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• 2011

Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.