• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.201-206
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• 2006

Genetic Algorithms have been known to provide near optimal solutions for various optimization problems in engineering. In this paper, we study the effect of gene order in genetic algorithms on the defining length of the schema with high fitness values. Its effect on the performance of genetic algorithms was also analyzed through two well known problems. A few gene reordering methods were proposed for graph partitioning and knapsack problems. Experimental results showed that genetic algorithms with gene reordering could find solutions of better qualities compared to the ones without gene reordering. It is very important to find proper reordering method for a given problem to improve the performance of genetic algorithms.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.960-968
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• 1995

In this paper we present a reordering scheme that could lead to efficient vectorization of the preconditioners for the large sparse linear systems arising from partial differential equations on the CRAY-2, This reordering scheme is a line version of the conventional red/black ordering. This reordering scheme, coupled with a variant of ILU(Incomplete LU) preconditioning, can overcome the poor rate of convergence of the conventional red/black reordering, if relatively large number of fill-ins were used. We substantiate our claim by conducting various experiments on the CRAY-2 machine. Also, the computation of the Frobenius norm of the error matrices agree with our claim.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.65-68
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• 2003

3GPP's RLC protocol specification adopted an error control scheme based on selective repeat ARQ. In 3GPP ARQ, distinctive windows are provide at transmitting and receiving stations so that those stations are prohibited to send or receive data PDU's out of window. An increase in window size enhances delay performance. Such an increase, however, raises the occupancy at reordering buffer, which results in a long reordering time. Aiming at suppressing the occupancy at reordering buffer, we propose a occupancy control scheme in this paper. In this scheme, a threshold is created in the receiving station's window and a data PDU out of the threshold (but within the window) is treated according to go back N ARQ. By the employment of the occupancy control scheme, the occupancy at the reordering buffer is apparently reduced, while the delay performance may be degraded due to the properties of go back N ARQ. We, thus, investigate the peak occupancy and mean delay performance by a simulation method. From numerical examples, we observe a trade-off in both performance measures and conclude that the peak occupancy is effectively reduced by setting a proper threshold under a constraint on mean delay performance.

• Convergence Security Journal
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• v.7 no.4
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• pp.115-121
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• 2007

Due on failures of communication nodes for the wireless and wired networks, mobile agents may be blocked even if there is available service in the networks. To solve it, we propose migration policy with reordering of the paths to guarantee the migration of mobile agents and the paper will provide the extension with the autonomous migration of mobile agents.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.34-36
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• 2004

최근의 Network Of Workstations (NOW) 시스템은 범용의 컴퓨팅 플랫폼으로 각광을 받고 있지만, 그 활용률은 여전히 사용자의 기대에 미치지 못하고 있다. 본 논문에서는 NOW 시스템의 활용률을 높이기 위한 방법으로 시스템의 부하 수준을 고려하여 프로세스 재 순서 (process reordering)를 사용하는 동시 스케쥴링 기법인 PROC (Process Reordering-based Coscheduling)을 제안한다. 그리고 자세한 시뮬레이션을 통해 PROC의 우수성을 검증한다.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.25 no.11
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• pp.1581-1593
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• 2001

An efficient variable-reordering method for finite element meshes is used and the effect of variable-reordering is investigated. For the element renumbering of unstructured meshes, Cuthill-McKee ordering is adopted. The newsy reordered global matrix has a much narrower bandwidth than the original one, making the ILU preconditioner perform bolter. The effect of variable reordering on the convergence behaviour of saddle point type matrix it studied, which results from P2/P1 element discretization of the Navier-Stokes equations. We also propose and test 'level(0) preconditioner'and 'level(2) ILU preconditioner', which are another versions of the existing 'level(1) ILU preconditioner', for the global matrix generated by P2/P1 finite element method of incompressible Navier-Stokes equations. We show that 'level(2) ILU preconditioner'performs much better than the others only with a little extra computations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.74-83
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• 2002

In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.750-758
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• 2013

In this paper, we introduce the low-density parity-check (LDPC) coded orthogonal frequency division multiplexing (OFDM) subframe reordering scheme for achieving equal combined power allocation in type I hybrid automatic repeat request (H-ARQ) systems and analyze the performance improvement by using the channel capacity. Also, it is confirmed that the layered decoding for subframe reordering scheme in H-ARQ systems gives faster convergence speed. It is verified from numerical analysis that a subframe reordering pattern having larger channel capacity shows better bit error rate (BER) performance. Therefore the subframe reordering pattern achieving equal combined power allocation for each subframe maximizes the channel capacity and outperforms other subframe reordering patterns. Also, it is shown that the subframe reordering scheme for achieving equal combined power allocation gives better performance than the conventional Chase combining scheme without increasing the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.8
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• pp.51-61
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• 2007

For provisioning reliable data transmission, the 3GPP RLC specification adopted a selective-repeat ARQ scheme assisted by a window-based admission control scheme. In the 3GPP ARQ, which is a member of the selective-repeat ARQ clan, inheres the reordering problem A long and irregular reordering time results in the degradation of throughput and delay performance, and may incur the overflow of the reordering buffer. Furthermore, the reordering time must be regulated to meet the requirements of some services which are loss-sensitive and delay-sensitive as well. Perceiving the reordering hazard, we propose an alternative, identified as snowball scheme, to the original admission control scheme of the 3GPP ARQ with aiming at deflating the occupancy of the reordering buffer. A unique feature of the snowball scheme is to reject a new DATA PDU if it is non-adjacent to any DATA PDU sojourning at the reordering buffer. Such an intentional rejection apparently reduces the occupancy of the reordering buffer while it may deteriorate the throughput and delay performance. Developing an analytical approximation method, we investigate the effect of snowball scheme on the saturated occupancy and throughput. Also, we, using a simulation method, evaluate the peak occupancy, normalized throughput and average delay in the practical environment. From the simulation results, we reveal that the snowball scheme is able to enhance occupancy performance as well as throughput performance compared with the original admission control scheme of the 3GPP ARQ.