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A Grouped Scan Chain Reordering Method for Wire Length Minimization  

Lee, Jeong-Hwan (Dept.of Computer, Sogang University)
Im, Jong-Seok (Dept.of Computer, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.8, 2002 , pp. 74-83 More about this Journal
Abstract
In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.
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