• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.61-68
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• 2002

지금까지 전자 디바이스의 솔더접합부에 대한 신뢰성 평가에 있어서는 열충격시험에 의한 평가가 주류를 이루었다. 그러나 최근 모바일 제품이 소형화/다기능화되고 고밀도실장에 대한 요구가 증가함에 따라 BGA/CSP와 같은 솔더볼을 사용하는 패키지가 표면실장의 주류를 이루게 되었으며, 솔더접합부에 대한 메커니컬 스트레스 수명이 요구되어지고 있다. BGA/CSP의 솔더접합부에 대한 신뢰성 평가는 하중을 가한 상태에서 데이지체인 패턴의 전기적 저항변화와 스트레인 게이지에 의한 스트레스-스트레인 커브에 의해 행해진다. 본 연구에서는 자체 개발한 PCB만능시험장치의 응용과 솔더접합부에 대한 메커니컬 스트레스의 동적거동을 평가한 소니의 실험자료를 소개하도록 한다.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.43-55
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• 2003

최근 IT산업의 발달과 그에 따른 전자부품기술의 발전이 가속화됨에 따라, 전자부품의 경박 단소화 및 고성능에 대한 요구는 전자패키지 (electronic package) 및 반도체기판(PKG substrate) 업체들로 하여금 고밀도의 입출력(I/O)과 우수한 열적, 전기적 특성을 보유하면서 높은 양산수율로 제품이 가격경쟁력을 갖도록 유도하고 있다. 이러한 경향에 따라 세계적인 반도체 회사(chip-maker)들은 더욱 혹독한 조건의 신뢰성 표준을 마련하여 제반 산업에 전반적인 적용을 요구하고 있으며, 환경친화 및 고주파, 고성능의 특성을 지닌 새로운 소재를 개발하도록 촉구하고 있는 실정이다. 반도체기판은 구성소재에 따라 구현되는 특성의 범위가 매우 크므로 우수한 특성의 소재를 반도체기판에 적용할 때 고객의 요구조건에 충분히 만족시킬 수 있을 것으로 기대된다. 따라서, 기판업계에서는 우수한 특성을 나타내는 원자재의 개발 및 수급이 절실하게 되었으며 급변하는 원자재의 기술 동향에 대한 분석은 향후 전자패키지 및 기판제품의 경쟁력을 향상시킬 수 있을 것이므로 본 연구에서는 최신 반도체기판 원자재의 기술 동향과 원자재의 특성을 분석하고자 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• 마이크로전자및패키징학회지
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• 제17권3호
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• pp.59-63
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• 2010

Immersion Sn plating was produced on Cu foil by distributing nano-sized diamonds (ND). The ND distributed on the coating surface broke the continuity of Sn-oxide layer, therefore leading to penetrate the molten solder through the oxide and retarding the wettability degradation during a reflow process. Furthermore, the ND in the Sn coating played a role of diffusion barrier for Sn atoms and decreased the growth rate of intermetallic compound ($Cu_6Sn_5$) layer during the solid-state aging. The study confirmed the importance of ND to improve the wettability and reliability of the Sn plating. Complete dispersion of the ND within the immersion Sn plating needs to be further developed for the electronic packaging applications.

• 마이크로전자및패키징학회지
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• 제25권2호
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• pp.1-8
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• 2018

In the soldering industry, a variety of lead-free solders have been developed as a part of restricting lead in electronic packaging. Sn-Ag-Cu (SAC) lead-free solder is regarded as one of the most superior candidates, owing to its low melting point and high solderability as well as the mechanical property. On the other hand, the mechanical property of SAC solder is directly influenced by intermetallic compounds (IMCs) in the solder joint. Although IMCs in SAC solder play an important role in bonding solder joints and impart strength to the surrounding solder matrix, a large amount of IMCs may cause poor strength, due to their brittle nature. In other words, the mechanical properties of SAC solder are of some concern because of the formation of large and brittle IMCs. As the IMCs grow, they may cause poor device performance, resulting in the failure of the electronic device. Therefore, new solder technologies which can control the IMC growth are necessary to address these issues satisfactorily. There are an advanced nanotechnology for microstructural refinement that lead to improve mechanical properties of solder alloys with nanoparticle additions, which are defined as nano-reinforced solders. These nano-reinforced solders increase the mechanical strength of the solder due to the dispersion hardening as well as solderability of the solder. This paper introduces the nano-reinforced solders, including its principles, types, and various properties.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• 대한기계학회논문집A
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• 제28권9호
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• 한국항공우주학회지
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• 제45권12호
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• pp.1048-1058
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• 2017

우주용 전장품의 주요 고장 메커니즘 중 하나는 발사진동에 의한 기판의 반복적인 굽힘에 의한 솔더 접합부 피로파괴이며, 상기의 잠재적 위험요소에 대해 피로수명 평가를 통한 조기진단의 필요성이 증대되고 있다. 종래 연구에서 제안된 솔더부 수명예측 기법은 실장기법이 달라지면 예측결과의 정확성을 장담할 수 없으며, 다수의 실장기법이 적용된 고집적 기판의 유한요소모델 구축에 많은 시간과 노력이 수반되는 단점이 있다. 본 연구에서는 기존 연구의 한계점 극복을 위해 우주용 전장품 구조 신뢰성 평가의 새로운 접근법으로 상용 신뢰성 수명예측 도구인 Sherlock을 이용한 기판의 수명예측을 실시하고 발사진동 수명시험을 통해 분석결과의 타당성을 검증하였다. 또한 전자소자 및 솔더 높이에 따른 피로수명 영향성 분석을 통해 Sherlock이 우주용 전장품의 구조 신뢰성 평가에 있어서 유용한 도구임을 입증하였다.

• 마이크로전자및패키징학회지
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• 제11권2호
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• pp.11-16
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• 2004

전자칩의 고집적화에 의해 전자기기들은 점점 소형화 되어가고 있으며, 이들 기기들에서 발생되는 열은 기기의 성능 저하뿐 아니라 수명을 단축시킨다. 본 연구에서는 효율적인 방열 위한 마이크로 히트싱크 제조를 위하여 멤브레인에 금속(금, 니켈, 구리)은 도금하는 무전해 도금 방법을 이용하였다. 무전해 도금은 폴리카보네이트 멤브레인을 sensitization과 activation 등의 전처리 후, 도금하고자 하는 금속염 수용액에 침적시켜 실행하였다. 무전해 도금에 의하여 제조된 각각의 마이크로피브릴의 열전달 특성과 방열량은 표면적이 가장 큰 니켈 마이크로피브릴에서 가장 우수하게 나타났다.

• Transactions on Electrical and Electronic Materials
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• 제15권4호
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• pp.221-225
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• 2014

Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.