• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.61-68
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• 2002

Thermal shock testing was used to evaluate reliability that appeared in the solder joints of electronic devices when they were subjected to thermal cycling. Recently, mobile devices have come smaller and multi-functional, with the increasing need for high-density packaging, BGA or CSP has become the main trend for surface mounting technology, and therefore mechanical stress life for solder joints in BGA/CSP type packages has required. Reliability of BGA/CSP solder joints was evaluated with electric resistivity change of daisy chain pattern and stress-strain curve measured using strain gage attached on the surface of PCB under mechanical impact loading. In this report, applications of PCB Universal Testing Machine we have developed and experimental datum of SONY estimating dynamic behavior of mechanical stress in BGA/CSP solder joints are introduced.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.43-55
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• 2003

As the development of If industries and their electronic device manufacturing technology have been accelerated recently, the request for electronic devices with small size, light weight, and high performance has been inducing that electronic package and substrate (PCB) companies have to develop substrates with low cost, high dense I/O, excellent thermal properties and electrical properties. Therefore, world-wide chip makers have been setting their own severe reliability standards and requiring their suppliers to keep specification and to develop green, high frequency and high-performing substrates. Because properties of substrates are dependent mainly on their constituent materials, the application of them showing superior properties is expected to satisfy the customer's requirement. Therefore, substrate companies should ensure the superiority of materials and assure their competitive capability of substrates by analyzing the latest trends of technology and properties of the materials.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.59-63
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• 2010

Immersion Sn plating was produced on Cu foil by distributing nano-sized diamonds (ND). The ND distributed on the coating surface broke the continuity of Sn-oxide layer, therefore leading to penetrate the molten solder through the oxide and retarding the wettability degradation during a reflow process. Furthermore, the ND in the Sn coating played a role of diffusion barrier for Sn atoms and decreased the growth rate of intermetallic compound ($Cu_6Sn_5$) layer during the solid-state aging. The study confirmed the importance of ND to improve the wettability and reliability of the Sn plating. Complete dispersion of the ND within the immersion Sn plating needs to be further developed for the electronic packaging applications.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.1-8
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• 2018

In the soldering industry, a variety of lead-free solders have been developed as a part of restricting lead in electronic packaging. Sn-Ag-Cu (SAC) lead-free solder is regarded as one of the most superior candidates, owing to its low melting point and high solderability as well as the mechanical property. On the other hand, the mechanical property of SAC solder is directly influenced by intermetallic compounds (IMCs) in the solder joint. Although IMCs in SAC solder play an important role in bonding solder joints and impart strength to the surrounding solder matrix, a large amount of IMCs may cause poor strength, due to their brittle nature. In other words, the mechanical properties of SAC solder are of some concern because of the formation of large and brittle IMCs. As the IMCs grow, they may cause poor device performance, resulting in the failure of the electronic device. Therefore, new solder technologies which can control the IMC growth are necessary to address these issues satisfactorily. There are an advanced nanotechnology for microstructural refinement that lead to improve mechanical properties of solder alloys with nanoparticle additions, which are defined as nano-reinforced solders. These nano-reinforced solders increase the mechanical strength of the solder due to the dispersion hardening as well as solderability of the solder. This paper introduces the nano-reinforced solders, including its principles, types, and various properties.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.12
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• pp.1048-1058
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• 2017

One of the failure mechanism of spaceborne electronics is a fatigue fracture on solder joint under launch random vibration. Thus, a necessity of early diagnosis through the fatigue life evaluation on solder joint arises to prevent such potential risk of failure. The conventional life prediction methods cannot assure the accuracy of life estimation results if the packaging type changes, and also requires much time and effort to construct the analysis model of highly integrated PCB with various packaging types. In this study, we performed life prediction of PCB based on a reliability and life prediction tool of sherlock as a new approach for evaluating the structural reliability on solder joint, and those prediction results were validated by fatigue tests. In addition, we also investigated an influence of solder height on the fatigue life of solder joint. These results indicated that the Sherlock is applicable tool for evaluating the structural reliability of spaceborne electronic.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.11-16
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• 2004

Electronic devices are getting smaller due to integration of electronic chip, and heat generated in electronic devices can cause loss of performance and/or reliability of the devices. In this research, metals such as gold, nickel and copper are plated onto a porous membrane by electroless plating method to make an efficient micro-heatsinks. Electroless plating includes sensitization and activation steps in pre-treatment steps. A polycarbonate(PC) membrane was sensitizied, activated and deposited in each metal solution for plating. Among manufactured microfibrils, heat transfer and radiation properties of Ni-microfibril with high surface area were more effective than those of $Au^-$ and Cu-microfibril.

• Transactions on Electrical and Electronic Materials
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• v.15 no.4
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• pp.221-225
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• 2014

Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.