• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.4
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• pp.612-616
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• 2012

This paper presents an active current regulator for LED driver IC. The proposed driver circuit is consists of DC-DC converter for supplying constant DC voltage to LED, active current regulator for compensating channel-to-channel current error from LED strings and feedback circuit for controlling duty ratio of the converter. The proposed active current regulator senses current of LED channels by equalizing both $V_{DS}$ and $V_{GS}$ at LED current control transistor. Because the proposed circuit directly measures the LED channel current without a sensing resistor and regulates all channel with same regulation loop, the power consumption and the current error are much small compared with previous works. The measured maximum efficiency of overall LED driver IC is approximately 94% and current error of LED channel-to-channel is under ${\pm}1.3%$. The proposed LED driver IC is fabricated Dongbu 0.35um BCD process.

• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.405-410
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• 1994

The purpose of this paper is to present the details of design procedure of a nonlinear regulator by Riemannian geometric approach and to applied it to the case of a double-effect evaporator. A nonlinear geometric model is proposed on a direct sum space of a state vector and a control vector as well as in the previous parers by the authors. The geometric model is derived by replacing the orthogonal straight coordinate axes of a linear system on the direct sum space with the curvilinear coordinate axes. The integral manifold of the geometric model becomes homeomorphic to that of fictitious linear system. For the geometric model a nonlinear regulator with a performance index is designed renewedly by the procedure of optimization. The construction method of the curvilinear coordinate axes on which the nonlinear system behaves as a linear system is discussed. To apply the above regulator theory to double-effect evaporators especially to the pilot plant at the University of Alberta, a suitable nonlinear model is determined by the plant dynamics. The optimal control law is derived through the calculation of the homeomorphism. As a result it is confirmed that the regulator is effective and superior to that of the conventional control.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.2
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• pp.331-336
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• 2012

This study was aimed at the design of the dies for the guide valve for the fuel pressure regulator using the computer simulation to shorten the period of production, on the basis of the process planning which was designed by the field experts. In the computer simulation, 'Deform-3d' and 'Eesy-DieOpt' have been used, which are the commercial process analysis and die design program. Through the process analysis, we could know the propriety of the forming process, the inner pressure of the die and the suitable fitting pressure between the insert and the sleeve which was not showing any positive tangential stresses in the insert. Through the simulation of die design, we could know the number of the stress ring, the diameter ratios, the stresses of the die, the shrink fitting tolerance and temperature in the condition of the already determined maximum outer die diameter of the multi-stage former. The validity of the die design using the computer simulation was analyzed by the experiments and the results were satisfactory. As the results of this study, the new and easy die design system for multi-forging has been developed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• Journal of Astronomy and Space Sciences
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• v.19 no.2
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• pp.107-122
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• 2002

Multi-body spacecraft attitude and configuration control formulations based on the use of collaborative control theory are considered. The control formulations are based on two-player, nonzero-sum, differential game theory applied using a Nash strategy. It is desired that the control laws allow different components of the multi-body system to perform different tasks. For example, it may be desired that one body points toward a fixed star while another body in the system slews to track another satellite. Although similar to the linear quadratic regulator formulation, the collaborative control formulation contains a number of additional design parameters because the problem is formulated as two control problems coupled together. The use of the freedom of the partitioning of the total problem into two coupled control problems and the selection of the elements of the cross-coupling matrices are specific problems ad-dressed in this paper. Examples are used to show that significant improvement in performance, as measured by realistic criteria, of collaborative control over conventional linear quadratic regulator control can be achieved by using proposed design guidelines.

• Journal of KSNVE
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• v.7 no.2
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• pp.301-310
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• 1997

This paper presents active noise control method to form the near-field quiet zone for passengers in an automobile. The actuator model including interior acoustic plant, speaker and amplifier is experimentally identified in forms of auto-regressive and moving average by means of least mean square algorithm, The digital controller is composed of the regulator and Kalman filter to be designed based on LQG (linear quadratic gaussian). If the actuator model is prefiltered with digital filter to be properly designed for concentrating control performance index on the frequency band of primary noise source, LQG design approach can be effectively applied for the design of headset controller. Experimental results demonstrate that near-field quiet zone showing about 10dB noise reduction at microphone position can be formed using the headset located at passenger seat.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.627-633
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• 2015

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.