• Information and Communications Magazine
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• v.30 no.11
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• pp.60-67
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• 2013

본 원고에서는 무선 전력 전송용 송수신 칩의 구조 및 설계 이슈에 대해서 설명하고, 각 구성 블록들의 동작 원리를 살펴본다. 또한, 무선 전력 전송의 효율을 향상시키기 위한 시스템 구조 및 Rectifier, DC-DC Converter, LDO Regulator, Power Amp 등에 대해서 기본적인 동작 원리부터 최근 설계 동향에 대해서 다룬다.

• Journal of Korean Society of Transportation
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• v.20 no.7
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• pp.177-183
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• 2002

Current state-of-the-art of VMS control is based upon simple knowledge-based inference engine with message set and each message's priority. And R&Ds of the VMS control are focused on the accurate detection and estimation of traffic condition of the subject roadways. However VMS display itself cannot achieve a desirable traffic allocation among alternative routes in the network In this context, VMS display strategy is the most crucial part in the VMS control. VMS itself has several limitations in its nature. It is generally known that VMS causes overreaction and concentration problems, which may be more serious in urban network than highway network because diversion should be more easily made in urban network. A feedback control algorithm is proposed in this paper to address the above-mentioned issues. It is generally true that feedback control approach requires low computational effort and is less sensitive to models inaccuracy and disturbance uncertainties. Major features of the proposed algorithm are as follows: Firstly, a regulator is designed to attain system optimal traffic allocation among alternative routes for each VMS in the network. Secondly, strategic messages should be prepared to realize the desirable traffic allocation, that is, output of the above regulator. VMS display strategy module is designed in this context. To evaluate Probable control benefit and to detect logical errors of the Proposed feedback algorithm, a offline simulation test is performed using real network in Daejon, Korea.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• Journal of IKEEE
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• v.20 no.4
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• pp.428-431
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• 2016

Power semiconductor devices had been producted with bipolar only processes, but Bipolar-CMOS-DMOS(BCD) processes have been adapted recently to fabricate these devices since most foundry companies have provided BCD processes instead of Bipolar only processes. In this study, Regulator and OP Amp are used as most popular design IPs and BCD processes for the designing are converted from bipolar only processes. Power Switching Sensor(PSS) ICs are designed specifically and fabricated on a silicon chip. The operation results of the packaged chip show the good matching with test results of the simulation.

• Journal of IKEEE
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• v.21 no.2
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• pp.154-157
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• 2017

This paper proposes the Low-Dropout regulator with two output. Each of the two output has feedback, and shared feedback loop. PMOS is added to solve the problem the occur when sharing the feedback loop. Thus eased the Load Transient Response. Also Using one of the bias citcuit and one of the pass transistor, Area is reduce by half compared to Existing Area that used to obtain output of two output.

• Journal of IKEEE
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• v.22 no.2
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• pp.384-392
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• 2018

A multiple-output LDO regulator is a good choice in terms of the efficiency in embedded systems requiring various supply voltages. A small feedback factor in LDO incurs the long settling time, resulting in large ripples in the time-multiplexing strategy. A new proposed topology enhances the settling time, and hence the ripples by incorporating the constant feedback factor with different reference voltages. The simulation results of a prototype design in a standard $0.35{\mu}m$ CMOS process verify that the proposed strategy enhances the settling time and ripple characteristic by more than doubled than a conventional circuit using the feedback factor of less than 0.4.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.26 no.2
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• pp.214-222
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• 2017

Maritime deck machinery relies heavily on the importation of components produced by overseas companies. Our research defines design parameters for hydraulic winch regulators used in maritime deck machinery. Using Amesim, we were able to conduct 1D modeling, and utilizing CFS then enabled us to create 3D models. These models were analyzed in our research for changes in pressure on each port that resulted from the regulator's spring constant and changes in the primary tension-compression field. Our research then analyzed alterations in traits caused by changes in the length of overlap between the spool and sleeve. Last but not least, our research analyzed the trait alteration resulting from changing the interval between the spool and sleeve. We believe the results of our research can be used to design a hydraulic winch regulator used in maritime deck machinery that does not require importation.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.4
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• pp.17-24
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• 2011

This paper presents a control scheme to cancel periodic disturbance with unknown frequency for optical disc drives. The control scheme consists of an output regulator and a frequency adaptive algorithm. Here, the frequency adaptive algorithm based on IMP plays a role in obtaining a frequency of periodic disturbance. The stability analysis of whole system and disturbance rejection performance are proven by the singular perturbation theory. The contribution of this paper are as follows. (1) There is no design constraints of the frequency range. (2) Ability for perfect disturbance rejection is preserved even with uncertain plant model.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.32-34
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• 2007

전자산업 부문의 친환경 대응이 이슈화 되면서 전자기기의 대기전력 소비감소를 위한 연구가 지속적으로 수행되고 있다. 전자기기의 대표적인 전원공급장치인 Switched Mode Power Supply(SMPS)의 경우 부하기기의 대기모드 시 극도로 낮은 출력전력에서 고효율을 달성해야 하는 요구가 높다. 특히 많은 SMPS들이 부하기기의 요구에 의하여 다출력 컨버터로 설계되어 있는데, 이러한 다출력 구조에서 대기모드 시 불필요한 출력을 절체함과 동시에 저전력에서 고효율을 내기가 쉽지 않다. 또한 다출력 구조로 인한 Cross Regulation 문제를 극복해야 하는 과제가 있다. 따라서 본 논문에서는 단일 컨버터 혹은 복수의 컨버터로 구성되어 있는 다출력 컨버터에서 대기전력 개선을 위한 Secondary Side Post Regulator(SSPR), 전류모드, Power Sequence 제어기술을 제안하고, 대기전력과 더불어 SSPR의 Cross Regulation 특성 개선을 검토하였다. 그리고 제안한 기술이 구현된 다출력 구조의 110W와 270W급 SMPS를 제작하여 회로의 타당성 및 우수성을 검증하였다.