• Title/Summary/Keyword: Regulator 설계

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A Design of Integrated Circuit for High Efficiency current mode boost DC-DC converter (고효율 전류모드 승압형 DC-DC 컨버터용 집적회로의 설계)

  • Lee, Jun-Sung
    • 전자공학회논문지 IE
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    • v.47 no.2
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    • pp.13-20
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    • 2010
  • This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

EMC Compatability Analysis on Geostationary Satellite (정지궤도 인공위성의 전자파 호환성 해석)

  • Chae, Tae-Byeong;Oh, Seung-Hyeub
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.12
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    • pp.1207-1215
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    • 2008
  • Satellite generates a complex electromagnetic noise by conducted and radiated coupling effect of the various electrical instruments. This noise may cause serious problems on the satellite system. To minimize the electromagnetic coupling effects and maintain the system safety margin, system noise reduction technique should be applied from the beginning of the system design. The COMS system is evaluated by measuring the conducted noise on system electrical power leads at PSR(Power Supply Regulator) and verifying a 6 dB system safety margin under the complex noise environment with current injection. The radiated noise due to the complex transmit antenna configuration is evaluated by integrating all unit-level RE measurement results, and the RF compatibility between spacecraft and launch vehicle is analyzed with the above estimations. This paper describes the COMS EMC compatibility analysis with respect to each unit level EMC test results, and RF compatibility analysis between spacecraft and launch vehicle. The analyzed results will be reflected on FM(Flight Model) EMC test.

A Scheduling Algorithm for Continuous Media (연속미디어를 위한 스케쥴링 알고리즘)

  • 유명련;안병철
    • Journal of Korea Multimedia Society
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    • v.4 no.5
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    • pp.371-376
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    • 2001
  • Since continuous media such as video and audio data are displayed within a certain time constraint, their computation and manipulation should be handled under limited condition. Traditional real-time scheduling algorithms cold be directly applicable, because they are not suitable for multimedia scheduling applications which support many clients at the same time. Rate Regulating Proportional Share Scheduling Algorithm based on the stride scheduler is a scheduling algorithm considered the time constraint of the continuous media. The stride schedulers, which are designed to general tasks, guarantee the fairness of resource allocation and predictability. The key concept of RRPSSA is a rate regulator which prevents tasks from receiving more resource than its share in a given period. But this algorithm loses fairness which is a strong point of the stride schedulers, and does not show graceful degradation of performance under overloaded situation. This paper proposes a new modified algorithm, namely Modified Proportional Share Scheduling Algorithm considering the characteristics of multimedia data such as its continuity and time dependency. Proposed scheduling algorithm shows graceful degradation of performance in overloaded situation and it reduces the scheduling violations up to 70% by maintaining the fair resource allocation. The number of context switching is 8% less than RRPSSA and the overall performance is increased.

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Developement of Electrical Load Testing System Implemented with Power Regenerative Function (회생전력 기능을 갖는 전기부하시험장치 개발)

  • Do, Wang-Lok;Chai, Yong-Yoong
    • The Journal of the Korea institute of electronic communication sciences
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    • v.11 no.2
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    • pp.179-184
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    • 2016
  • The electrical load testing system developed from this study was designed to control rated-capacity-testing or variable-load-testing in an active and precise manner and save electric energy during testing, and also to convert the saved electric energy through the electrical load testing system to grid line. As for the device under testing, it was designed to be applied to not only transformer, rectifier, voltage regulator, inverter which require grid voltage source but, also applied to electric power, aerogenerator, photovoltaic, hybrid generator, battery, etc. which do not require grid voltage source. The system was designed to return the power consumed during the testing to the grid line by connecting the synchronizing pwm inverter circuit to the grid voltage source, and was also made to enable the being-tested system from disuse of approximately 93.4% energy when compared to the conventional load testing system which has used the passive resistor.

A Design of Multi-Channel Capacitive Touch Sensing ASIC for SoC Applications in 0.18 ${\mu}m$ CMOS Process (0.18 ${\mu}m$ CMOS 공정을 이용한 SoC용 정전 용량형 멀티 채널 터치 센싱 ASIC의 설계)

  • Nam, Chul;Pu, Young-Gun;Park, Joon-Sung;Hong, Seong-Hwa;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.26-33
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    • 2010
  • This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.

A Modified Proportional Scheduler and Evaluation Method (수정 비례 지분 스케쥴러 및 평가법 설계)

  • 김현철;박정석
    • Journal of Internet Computing and Services
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    • v.3 no.2
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    • pp.15-26
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    • 2002
  • Since multimedia data such as video and audio data are displayed within a certain time constraint, their computation and manipulation should be handled under limited condition. Traditional real-time scheduling algorithms could net be directly applicable, because they are not suitable for multimedia scheduling applications which support many clients at the same time. Rate Regulating Proportional Share Scheduling Algorithm is a scheduling algorithm considered the time constraint of the multimedia data. This scheduling algorithm uses a rate regulator which prevents tasks from receiving more resource than its share in a given period. But this algorithm loses fairness, and does not show graceful degradation of performance under overloaded situation, This paper proposes a new modified algorithm. namely Modified Proportional Share Scheduling Algorithm considering the characteristics of multimedia data such as its continuity and time dependency, Proposed scheduling algorithm shows graceful degradation of performance in overloaded situation and the reduction in the number of context switching, Furthermore, a new evaluation method is proposed which can evaluate the flexibility of scheduling algorithm.

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A Scheduler for Multimedia Data and Evaluation Method (멀티미디어 데이터를 위한 스케쥴러 및 평가법 설계)

  • 유명련;김현철
    • Journal of the Institute of Convergence Signal Processing
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    • v.3 no.2
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    • pp.1-7
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    • 2002
  • Since multimedia data such as video and audio data are displayed within a certain time constraint, their computation and manipulation should be handled under limited condition. Traditional real-time scheduling algorithms could not be directly applicable, because they are not suitable for multimedia scheduling applications which support many clients at the same time. Rate Regulating Proportional Share Scheduling Algorithm is a scheduling algorithm considered the time constraint of the multimedia data. This scheduling algorithm uses a rate regulator which prevents tasks from receiving more resource than its share in a given period. But this algorithm loses fairness, and does not show graceful degradation of performance under overloaded situation. This paper proposes a new modified algorithm, namely Modified Proportional Share Scheduling Algorithm considering the characteristics of multimedia data such as its continuity and time dependency. Proposed scheduling algorithm shows graceful degradation of performance in overloaded situation and the reduction in the number of context switching. Furthermore, a new evaluation method is proposed which can evaluate the flexibility of scheduling algorithm.

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Application of Adaptive Control Theory to Nuclear Reactor Power Control (적응제어 기법을 이용한 원자로 출력제어)

  • Ha, Man-Gyun
    • Nuclear Engineering and Technology
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    • v.27 no.3
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    • pp.336-343
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    • 1995
  • The Self Tuning Regulator(STR) method which is an approach of adaptive control theory, is ap-plied to design the fully automatic power controller of the nonlinear reactor model. The adaptive control represent a proper approach to design the suboptimal controller for nonlinear, time-varying stochastic systems. The control system is based on a third­order linear model with unknown, time-varying parameters. The updating of the parameter estimates is achieved by the recursive extended least square method with a variable forgetting factor. Based on the estimated parameters, the output (average coolant temperature) is predicted one-step ahead. And then, a weighted one-step ahead controller is designed so that the difference between the output and the desired output is minimized and the variation of the control rod position is small. Also, an integral action is added in order to remove the steady­state error. A nonlinear M plant model was used to simulate the proposed controller of reactor power which covers a wide operating range. From the simulation result, the performances of this controller for ramp input (increase or decrease) are proved to be successful. However, for step input this controller leaves something to be desired.

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High Efficiency Magnetic Resonance Wireless Power Transfer System and Battery Charging Chip (자기 공진 방식의 고효율 무선 전력 전송 시스템 및 배터리 충전 칩)

  • Youn, Jin Hwan;Park, Seong Yeol;Choi, Jun Rim
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.6
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    • pp.43-49
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    • 2015
  • In this paper, we propose enhanced wireless power transfer system based on magnetic resonance for portable electronic device charging. Resonators were designed and fabricated for efficiency improvement and miniaturization through electromagnetism simulation using HFSS(High Frequency Structure Simulator). Impedance matching network is employed to minimize reflections that is caused by difference between input impedance and output impedance. Receiver IC that consist of rectifier and Low Drop Out(LDO) regulator were designed and fabricated to reduce power loss. This chip is implemented in $0.35{\mu}m$ BCD technology. A maximum overall efficiency of 73.8% is determined for the system through experimental verification.

A Study on The Design of China DSRC System SoC (중국형 DSRC 시스템 SoC 설계에 대한 연구)

  • Shin, Dae-Kyo;Choi, Jong-Chan;Lim, Ki-Taeg;Lee, Je-Hyun
    • 전자공학회논문지 IE
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    • v.46 no.4
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    • pp.1-7
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    • 2009
  • The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.