• Title/Summary/Keyword: Register Control

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A Study on a Hardware Folw-Chart and Hardware Description Language for FSM (FSM 설계를 위한 하드웨어 흐름도와 하드웨어 기술 언어에 관한 연구)

  • Lee, Byung-Ho;Cho, Joong-Hwee;Chong, Jong-Wha
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.4
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    • pp.127-137
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    • 1989
  • This paper describes hardware flow-chart and SDL-II, which are register-transfer level, to automate logic design. Hardware flow-chart specifies behavioral and structural charaterstics of generalized FSMs (Finite State Machine) usin the modified ASM (Algorithmic State Machnine) design techniques. SDL-II describes the hardware flow-chat which specifies the control and the data path of ASIC(Application Specific IC). Also many examples are enumerated to illustrate the features of hardware flow-chart and SDL-II.

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A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

  • Lim, Shin-Il;Kim, Jin Woo;Yoon, Kwang-Sub;Lee, Sangmin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.2
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    • pp.108-113
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    • 2013
  • This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

The research of restoration paper(Hanji) as the solution of damage in the bees-waxed volume of the Annals of Joseon Dynasty (조선왕조실록 밀납본 손상 복원을 위한 복원용지 탐색)

  • Seo, Jin-ho;Jeong, So-young;Jeong, Seon-hwa
    • 보존과학연구
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    • s.28
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    • pp.5-19
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    • 2007
  • The annals of Joseon Dynasty is the most valuable resource containing the record of Korean history and has been known as one of the UNESCO's Memory of the World Register. There was a period that the annals of Joseon Dynasty was used with beeswax to control pests. It is considered as the prior reason of damage on the annals of Joseon Dynasty. Therefore, in this study we examined the restoration paper(Hanji) as the solution of damage in the waxed volume of the annals of Joseon Dynasty. FT-IR spectrometer was used to examine traditional paper inside and outside of Korea and accelerated artificial aging paper. As a result of FT-IR analysis, spectrum did not showed its big difference in all paper used in this study. However, there was a different spectrum in paper which was made with not Broussonetia kazinoki, but Echinochloa crus-galli var. frumentacea and Dioscorea batatas. Among traditional papers in various countries, spectrum of Korean paper showed the most similarity from the annals of Joseon Dynasty. In comparison between accelerated artificial aging paper and waxed volume, we could identify the change of spectrum affected by the damage.

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Effect of precooling on pain during local anesthesia administration in children: a systematic review

  • Tirupathi, Sunny Priyatham;Rajasekhar, Srinitya
    • Journal of Dental Anesthesia and Pain Medicine
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    • v.20 no.3
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    • pp.119-127
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    • 2020
  • This study was conducted to determine how precooling reduces the subjective reported pain and objective pain and to evaluate the effectiveness of precooling the injection site before administration of local anesthesia in children. Electronic databases (PubMed, Ovid SP, Cochrane Central Register of Controlled Trials) were searched for publications from 1980 to 2020. Studies were screened for titles and abstracts, followed by full-text evaluation of included reports. Six studies were included in this systematic review. The primary outcome evaluated was the pain perception or the subjective pain reported by the child receiving the injection. The secondary outcome evaluated was objective pain evaluated in each study. Among 5 studies that evaluated child reported pain scores on a visual analogue scale (VAS), 4 studies reported lower scores in the precooling group and one study reported a higher VAS score in the precooling group than in children treated with 20% benzocaine topical anesthesia. Among 6 studies that evaluated the pain reaction of children by Sound Eye Motor (SEM) score, 4 studies reported a lower SEM score in the precooling group, one study reported no significant difference between the precooling and control groups, and one study reported higher SEM scores in the precooling group than in children treated with 20% benzocaine topical anesthesia. Within the limits of this systematic review, evidence suggests that precooling the injection site with ice can be an effective adjunct to topical anesthesia in reducing both subjective and objective pain during local anesthesia administration in children.

A Simultaneous Hardware Resource Allocation and Binding Algorithm for VLSI Design (VLSI 설계를 위한 동시수행 하드웨어 자원 할당 및 바인딩 알고리듬)

  • 최지영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10A
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    • pp.1604-1612
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    • 2000
  • This paper proposes a simultaneous hardware resource allocation and binding algorithm for VLSI design. The proposed algorithm works on scheduled input graph and simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Also, the register allocation is especially executes the allocation optima us-ing graph coloring techniques. Therefore the overall resource is reduced. This paper shows the effectiveness of the proposed algorithm by comparing experiments to determine number of functional unit in advance or to separate executing allocation and binding of existing system.

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The Resisting Body: Figurative Painting as a Means to Register Social Protest in Malaysian Art (저항하는 몸: 말레이시아 미술에서 사회적 저항의 수단으로서 형상회화)

  • Fan, Laura
    • The Journal of Art Theory & Practice
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    • no.8
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    • pp.185-215
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    • 2009
  • In Malaysia, figurative painting has increasingly become a means for artists to pose questions about presumptions of power and assumptions of history. The body, its potentially breached boundaries and defenses, forms an integral component of the battle for political influence. The degree of control over one's own and other people's bodies has become a measuring stick to determine the power of potential political leaders. Anxiety about boundaries and access to powerful bodies is intertwined with the questions of who has the right to hold power; the relevance of moral bodies and of what comprises an ideal self or selves. These questions are raised in intriguing ways in contemporary Malaysian art. While eschewing a direct take on current politics, Malaysian artists have increasingly turned to the body to address issues in Malaysian history, culture and the distribution of power. This paper will explore some works by three artists in particular, Wong Hoy Cheong, Nadiah Bamadhaj and Ahmad Fuad Osman use the figure to problematise dominant narratives in Malaysian history. Their work variously challenge political, racial and gender hierarchies and in so doing, reveal them as social constructions.

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Simulation and Synthesis of RISC-V Processor (RISC-V 프로세서의 모의실행 및 합성)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.1
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    • pp.239-245
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    • 2019
  • RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

Real-time Processing Method for Windows OS Using MSR_FSB_FREQ Control (MSR_FSB_FREQ 제어를 이용한 윈도우 운영체제에 실시간 처리 방법)

  • Kim, Jong Jin;Lee, Sang Gil;Lee, Cheol Hoon
    • Journal of Korea Multimedia Society
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    • v.24 no.1
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    • pp.95-105
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    • 2021
  • In the case of laptops and tablet PC's that replace desktop, it uses the Windows operating system to provide various functions depending on operating system dependency, the Windows operating system does not support real-time processing because it uses multi-level feedback queue scheduling that extends round-robin scheduling. Also, since the initial value of Local APIC Counter can not be obtained from the Windows 8, the real-time processing function provided through the existing RTiK does not work. In this paper, we calculate Local APIC Counter value by using MSR_FSB_FREQ register to support real-time processing function on tablet PC's. We designed and implemented RTiK+, which provides real-time processing function to guarantee the periodicity by calculating the operation time of accurate timer. In order to verify and evaluate the performance of the implemented the RTiK+, the period was measured by using the Read Time-Stamp Counter(RDTSC) instruction and it was confirmed that it operates normally at 1ms and 0.1ms period.

Herbal Medicine for the Treatment of Non-Erosive Reflux Disease: A Systematic Review and Meta-Analysis Protocol

  • Minjeong Kim;Chaehyun Park;Jae-Woo Park;Jinsung Kim;Seok-Jae Ko
    • The Journal of Internal Korean Medicine
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    • v.44 no.6
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    • pp.1176-1185
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    • 2023
  • Introduction: Non-erosive reflux disease (NERD) is the most common subtype of gastroesophageal reflux disease (GERD). This study aims to synthesize evidence on the efficacy and safety of various herbal medicines for the treatment of NERD. Methods and analysis: Ten electronic databases will be examined: MEDLINE (via PubMed), Cochrane Central Register of Controlled Trials, Embase, Allied and Complementary Medicine Database, China National Knowledge Infrastructure Database, Citation Information by Nii, Korean Medical Database, Korean Studies Information Service System, National Digital Science Library, and Oriental Medicine Advanced Searching Integrated System. All randomized controlled trials published from inception to May 2023 that meet the eligibility criteria will be selected. Two independent researchers will extract data, such as publication year, study design, intervention details, outcome measures, main results, and adverse events. The risk of bias and quality of evidence will be assessed, and subgroup analyses will be performed according to the type of control intervention and herbal medicine. The analysis process will be conducted using Review Manager 5.4 software. Discussion: This review will present a summary and rationale for herbal medicine's effectiveness in treating NERD. The findings of this review can help those who want to apply herbal medicine to the treatment of NERD.

12-bit SAR A/D Converter with 6MSB sharing (상위 6비트를 공유하는 12 비트 SAR A/D 변환기)

  • Lee, Ho-Yong;Yoon, Kwang-Sub
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1012-1018
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    • 2018
  • In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.