• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.485-486
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• 2006

This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.193-198
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• 2020

The various uses of the Convolutional Neural Network technology are accelerating the evolution of the computing area, but the opposite is causing serious hardware performance shortages. Neural network accelerators, next-generation memory device technologies, and high-bandwidth memory architectures were proposed as countermeasures, but they are difficult to actively introduce due to the problems of versatility, technological maturity, and high cost, respectively. This study proposes DRAM-based main memory technology that enables read operations to be completed without waiting until the end of the refresh operation using pre-stored XOR bit values, even when the refresh operation is performed in the main memory. The results showed that the proposed technique improved performance by 5.8%, saved energy by 1.2%, and improved EDP by 10.6%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.31-38
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• 2010

This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Magazine of the Korea Concrete Institute
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• v.15 no.4
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• pp.41-47
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• 2003

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.947-950
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• 2008

This paper reports of traceable and repeatable time resolved colorimetric measurements of the luminance- and colour variation occurring during the frame refresh period of FPD's. During one frame period a number of measurements are performed, and for the dynamic artifacts a simulated smooth pursuit eye tracking algorithm is included.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1214-1221
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• 2006

Header compression scheme is suggested as a solution to reduce the inefficient overhead of general packet stream data. Especially, it is shown that there are more overhead rate for real-time media stream links such as voice because of its short payload size, and it is possible to get higher bandwidth efficiency using the header compression scheme. There are two kinds of error recovery in header compression such as Periodic Header Refresh(PHR) and Header Request(HR) schemes. In this paper, we analyze the performance of these two compression recovery schemes, and some results such as the overhead rate, bandwidth gain and bandwidth efficiency(BE) are presented.

• The Journal of the Acoustical Society of Korea
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• v.31 no.7
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• pp.435-440
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• 2012

We propose optimal contexts for context-adaptive coding of stereo parameters in parametric stereo (PS) of enhanced aacPlus. For the quantized indexes of stereo parameters, 8 context candidates were proposed based on the index values and their combinations adjacent to a source index in the time-stereo band domain, where the time-stereo band region was further divided into 4 regions based on refresh/non-refresh frames and stereo bands. The optimal contexts for each region were proposed by experiments, which are expected to be used for context-adaptive coding of PS for improved performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.720-726
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• 2009

There are coexisting various kinds of data in the large scale database system, the maintenance problem of freshness of data is emerging important issue that provide correctness and usefulness information to users. Most solution of this problem depends on how execute effectively required refreshing query within timely time. In this paper, we propose the refreshing scheduling algorithm to retain the freshness of data and fairness of starvation of requested refresh queries. Our algorithm recompute a rate of goal refreshing a every period to assign execution time of requested refreshing query so that we can keep the freshness and fairness of data by using proposed algorithm. We implement the web sites to showing the results of refreshing process of dynamic and semi-dynamic and static data.