• 제목/요약/키워드: Reference Frequency

검색결과 1,631건 처리시간 0.03초

Feedback을 가진 P.V.M.방식 Chopper 회로에 관한 연구 (A Study on Pulse Frequency Modulated Chopper with Feedback)

  • 박민호;전희종
    • 전기의세계
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    • 제26권3호
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    • pp.63-68
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    • 1977
  • In this paper, the theory of pulse frequency modulated DC/DC power converter to obtain constant output voltage for all input voltage changes is discussed. The switch controller consisting of integrator and comparator determines the ON time of power switch-Thyristor-by the error between the load voltage and a load reference voltage. Resulting voltage and current waveforms have been studied theoretically in detail and verified experimentally for a resistive and inductive load condition. State equations for voltages and currents using binary logic variables are computed by digital computer. Comparison of these withe oscillograms obtained from an experimental model shows very close agreement.

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발전계통의 신속도 산정에 관한 연구 (A Study on the Generating System Reliability Evaluation)

  • 김준현;황갑주;송석하
    • 대한전기학회논문지
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    • 제32권3호
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    • pp.69-75
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    • 1983
  • This paper presents a improved algorithm for the generating capacity reliability evaluation using the frequency and duration approach. One of the specific feature of this algorithm is that propose the cumulative state load model via analytic expression of load duration curve and cumulative load frequency characteristic in conside ration of daily peak load. The paper illustrates the utilization of the proposed algorithm in actual system studies using the generating system of KEPCO. The results presented will provide a valuable reference for maintaining and planing the generating system.

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2중주파 합성시험회로의 TRV 패턴 분류 및 파라미터 계산 방법 (TRV Pattern Classification and Parameter Calculation Method for Double-Frequency Synthetic Test Circuit)

  • 이용한
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 하계학술대회 논문집 A
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    • pp.587-589
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    • 2004
  • In this paper analytical pattern classification of TRV waves created by double-frequency synthetic test circuit was proposed. According to the classified patterns of the TRV wave, calculation methods of 3 reference lines and 4 parameters characterizing the TRV wave wire proposed. These methods can be utilized to optimize test facility and to standardize test quality.

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단일주파수 GNSS 수신기를 위한 전리층 모델 비교 (Comparison of Ionosphere Models for Single Frequency GNSS Receiver)

  • 이창문;박관동
    • 한국측량학회:학술대회논문집
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    • 한국측량학회 2010년 춘계학술발표회 논문집
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    • pp.147-150
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    • 2010
  • Ionopheric deley is the largest error sources in GNSS positining. The single frequency receiver user needs an ionospheric model like the Klobuchar model or NeQuick model to eliminate the ionospheric error. In this study we estimated VTEC(Vertical Total Electron Content) over DAEJ station using the two models in each season. We compared the results with Global Ionosphere Maps and International Reference Ionosphere model predictions. As a result, the NeQuick model was more accurate than Klobuchar model.

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고속 혼성모드 집적회로를 위한 온-칩 CMOS 전류 및 전압 레퍼런스 회로 (On-Chip Full CMOS Current and Voltage References for High-Speed Mixed-Mode Circuits)

  • 조영재;배현희;지용;이승훈
    • 전자공학회논문지SC
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    • 제40권3호
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    • pp.135-144
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    • 2003
  • 본 논문에서는 고속 혼성모드 집적회로를 위한 온-칩(on-chip) CMOS 전류 및 전압 레퍼런스 회로를 제안한다. 제안하는 전류 레퍼런스 회로는 기존의 전류 레퍼런스 회로에서 부정확한 전류 값을 조정하기 위해 주로 사용되는 아날로그 보정 기법과는 달리 디지털 영역에서의 보정 기법을 사용한다. 또한, 제안하는 전압 레퍼런스 회로는 고속으로 동작하는 혼성모드 집적회로의 출력단에서 발생할 수 있는 고주파수의 잡음 성분을 최소한으로 줄이기 위해 고주파 신호 성분에 대해 작은 출력 저항을 볼 수 있는 구조의 레퍼런스 전압 구동회로를 사용한다. 이 레퍼런스 전압 구동회로는 전력 소모 및 칩 면적을 최소화하기 위해서 저 전력의 증폭기와 크기가 작은 온-칩 캐패시터를 사용하여 구현하였다. 제안하는 레퍼런스 회로는 0.18 um n-well CMOS 공정으로 설계 및 제작되었으며, 250 um x 200 um의 면적을 차지한다. 칩 제작 및 측정결과, 제안하는 전류 및 전압 레퍼런스 회로는 공급 전압 및 온도의 변화에 대해서 각각 2.59 %/V와 48 ppm/℃의 변화율을 보인다.

High-speed CMOS Frequency Divider with Inductive Peaking Technique

  • Park, Jung-Woong;Ahn, Se-Hyuk;Jeong, Hye-Im;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제15권6호
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    • pp.309-314
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    • 2014
  • This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

가변주파수에 있어서 유도전동기의 특성도식 산정법에 관해서 제1보 (A Study on the Current-diagram Method for Calculating Induction Motor Characteristics with Adjustable Frequency)

  • 박민호
    • 전기의세계
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    • 제17권3호
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    • pp.29-38
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    • 1968
  • The development of the frequency converter using semiconductor enables to easily control the speed of A.C. motors. It is now technically possible and economically feasible to provide them with power at variable frequency, using silicon-controlled-rectifier (or thyristor) inverters. In such a case, if an induction motor is to be operated efficiently over a wide speed range, it must be supplied from a variable-frequency source whose frequency is adjustable over a range similar to that required for the motor speed. It is desired to observe how several characteristics are changed such as primary current, torque-speed, etc. Although the characteristics could be obtained by means of the conventional method, it requires very complicated calculation. It is assumed that the charateristics above are easily investigated by means of current diagram method from variable circuit constants relating to the motor which is designed in rated frequency. In this paper, the results of the study on the current-diagram method and its application are described as follows; (1) In order to discuss the construction of current diagram, the equation of the stator current with adjustable frequency was derived for applying the Current Diagram Method. (2) The radius, the center of the current circle and current vector locus at any desired frequency could be easily determined with the aid of both above mentioned equation and the standard current diagram at reference frequency. (3) This method could be applicable to the various types of Induction Motors, and this paper has dealt with its application to the capacitor, split-phase and 2-phase types of motors.

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동작온도에 무관한 Frequency-to-Voltage 변환 회로 (Temperature Stable Frequency-to-Voltage Converter)

  • 최진호;유영중
    • 한국정보통신학회논문지
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    • 제11권5호
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    • pp.949-954
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    • 2007
  • 본 논문에서는 CMOS 공정을 이용하여 동작온도에 무관한 FVC(Frequency-to-Voltage Convener) 회로를 제안한다. FVC는 FLL(Frequency Locked Loop)의 핵심 회로로서 주파수 신호를 전압신호로 변환하는 회로이다. FLL 회로는 PLL(Phase-Locked Loop) 회로 같이 고정된 주파수 신호를 생성하는 회로지만, PLL과는 달리 위상비교기, charge pump, 저역 필터 등이 필요치 않아 간단히 회로를 구성할 수 있다. FVC 회로의 설계는 $0.25{\mu}m$ CMOS 공정을 이용하였다. 설계되어진 회로의 입력 주파수는 70MHz에서 140MHz를 사용하였다. 회로의 시뮬레이션 결과 동작 온도가 $0^{\circ}C$에서 $75^{\circ}C$까지 변화할 때 변환된 출력 전압의 변화는 상온에 비하여 ${\pm}2%$이내였다.

Fractional-N PLL (Phase-Locked Loop) 주파수 합성기 설계 (Fractional-N PLL Frequency Synthesizer Design)

  • 김선철;원희석;김영식
    • 대한전자공학회논문지TC
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    • 제42권7호
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    • pp.35-40
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    • 2005
  • 본 논문에서는 900MHz 대역 중저속 무선 통신용 칩에 이용되는 3차 ${\Delta}{\sum}$ modulator를 사용한 Fractional-N PLL 주파수 합성기를 설계 및 제작하였다 우수한 위상노이즈 특성을 얻기 위해 노이즈 특성이 좋은LC VCO를 사용하였다. 그리고 고착시간을 줄이기 위해서 Charge Pump의 펌핑 전류를 주파수 천이 값에 따라 조절할 수 있도록 제작하였고 PFD의 참조 주파수를 3MHz까지 높였다. 또한 참조 주파수를 높이는 동시에 PLL의 최소 주파수 천이 간격을 10KHz까지 줄일 수 있도록 하기위하여 36/37 Fractional-N 분주기를 제작하였다. Fractional Spur를 줄이기 위해서 3차 ${\Delta}{\sum}$ modulator를 사용하였다. 그리고 VCO, Divider by 8 Prescaler, PFD, 및 Charge Pump는 0.25um CMOS공정으로 제작되었으며, 루프 필터는 외부 컴포넌트를 이용한 3차RC 필터로 제작되었다. 그리고 Fractional-N 분주기와 3차 ${\Delta}{\sum}$ modulator는 VHDL 코드로 작성되었으며 Xilinx Spartan2E을 사용한 FPGA 보드로 구현되었다. 측정결과 PLL의 출력 전력은 약 -11dBm이고, 위상노이즈는 100kHz offset 주파수에서 -77.75dBc/Hz이다. 최소 주파수 간격은 10kHz이고, 최대 주파수 천이는 10MHz이고, 최대 주파수 변이 조건에서 고착시간은 약 800us이다.

엔진 고공 시험에서 연료 유량 측정용 터빈 유량계의 측정 불확도 분석 (Measurement Uncertainty Analysis of a Turbine Flowmeter for Fuel Flow Measurement in Altitude Engine Test)

  • 양인영
    • 한국유체기계학회 논문집
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    • 제14권1호
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    • pp.42-47
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    • 2011
  • Measurement uncertainty analysis of fuel flow using turbine flowmeter was performed for the case of altitude engine test. SAE ARP4990 was used as the fuel flow calculation procedure, as well as the mathematical model for the measurement uncertainty assessment. The assessment was performed using Sensitivity Coefficient Method. 11 parameters involved in the calculation of the flow rate were considered. For the given equipment setup, the measurement uncertainty of fuel flow was assessed in the range of 1.19~1.86 % for high flow rate case, and 1.47~3.31 % for low flow rate case. Fluctuation in frequency signal from the flowmeter had the largest influence on the fuel flow measurement uncertainty for most cases. Fuel temperature measurement had the largest for the case of low temperature and low flow rate. Calibration of K-factor and the interpolation of the calibration data also had large influence, especially for the case of very low temperature. Reference temperature, at which the reference viscosity of the sample fuel was measured, had relatively small contribution, but it became larger when the operating fuel temperature was far from reference temperature. Measurement of reference density had small contribution on the flow rate uncertainty. Fuel pressure and atmospheric pressure measurement had virtually no contribution on the flow rate uncertainty.