• 제목/요약/키워드: Reference Bandwidth

검색결과 175건 처리시간 0.026초

Adaptive Bandwidth Algorithm for Optimal Signal Tracking of DGPS Reference Receivers

  • Park, Sang-Hyun;Cho, Deuk-Jae;Seo, Ki-Yeol;Suh, Sang-Hyun
    • 한국항해항만학회지
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    • 제31권9호
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    • pp.763-769
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    • 2007
  • A narrow loop noise bandwidth method is desirable to reduce the error of raw measurements due to the thermal noise. However, it degrades the performance of GPS initial synchronization such as mean acquisition time. And it restricts the loop noise bandwidth to a fixed value determined by the lower bound of the allowable range of carrier-to-noise power ratio, so that it is difficult to optimally track GPS signal. In order to make up for the weak points of the fixed-type narrow loop noise bandwidth method and simultaneously minimize the error of code and carrier measurements, this paper proposes a stepwise-type adaptive bandwidth algorithm for DGPS reference receivers. In this paper, it is shown that the proposed adaptive bandwidth algorithm can provide more accurate measurements than those of the fixed-type narrow loop noise bandwidth method, in view of analyzing the simulation results between two signal tracking algorithms. This paper also carries out sensitivity analysis of the proposed adaptive bandwidth algorithm due to the estimation uncertainty of carrier-to-noise power ratio. Finally the analysis results are verified by the experiment using GPS simulator.

선형 시스토릭 어레이를 이용한 완전탐색 블럭정합 이동 예측기의 구조 (A linear systolic array based architecture for full-search block matching motion estimator)

  • 김기현;이기철
    • 한국통신학회논문지
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    • 제21권2호
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    • pp.313-325
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    • 1996
  • This paper presents a new architecture for full-search block-matching motion estimation. The architecture is based on linear systolic arrays. High speed operation is obtained by feeding reference data, search data, and control signals into the linear systolic array in a pipelined fashion. Input data are fed into the linear systolic array at a half of the processor speed, reducing the required data bandwidth to half. The proposed architecture has a good scalability with respect to the number of processors and input bandwidth when the size of reference block and search range change.

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A Low Jitter and Fast Locking Phase-Lock Loop with Adaptive Bandwidth Controller

  • Song Youn-Gui;Choi Young-Shig
    • Journal of information and communication convergence engineering
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    • 제3권1호
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    • pp.18-22
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    • 2005
  • This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

원통형 자성체를 이용한 고이득 및 광대역 안테나 설계 (High gain and broad bandwidth antenna design using cylindrical magneto material)

  • 이지철;민경식
    • 한국항해항만학회지
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    • 제34권1호
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    • pp.21-26
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    • 2010
  • 본 논문은 패치 안테나의 급전선 주위에 원통형 자성체을 이용하여 안테나의 고이득 및 광대역 안테나 설계법에 대해서 기술한다. 안테나의 고이득 설계를 위해서 급전선 주위에 생기는 자기장과 원통형 자성체 주위에 생기는 자기장을 결합시켜 급전선에 강한 전류를 유도시키는 방법을 사용하였고, 안테나의 광대역 설계를 위해서 shorting 스티브를 추가한 PIFA의 원리를 적용하여 설계하였다. 단일 원통형 자성체의 경우, 참고 안테나와 비교하여 3.96 dB 이득이 증가하였으나 대역폭 특성은 개선되지 않았다. 이중 원통형 자성체의 경우, 참고 안테나와 비교하여 이득은 약 10 dB 개선되었으며, -10 dB 이하 대역폭은 700 MHz(50 MHz~750 MHz)로써 광대역 특성을 가지는 안테나를 설계하였다.

BLOCK-BASED ADAPTIVE BIT ALLOCATION FOR REFENCE MEMORY REDUCTION

  • Park, Sea-Nae;Nam, Jung-Hak;Sim, Dong-Gy;Joo, Young-Hun;Kim, Yong-Serk;Kim, Hyun-Mun
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 2009년도 IWAIT
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    • pp.258-262
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    • 2009
  • In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

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묵시적 가중 예측기법을 이용한 저 메모리 대역폭 인터 예측기 설계 (Design of a Low Memory Bandwidth Inter Predictor Using Implicit Weighted Prediction Technique)

  • 김진영;류광기
    • 한국정보통신학회논문지
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    • 제16권12호
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    • pp.2725-2730
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    • 2012
  • 본 논문에서는 H.264/AVC 인코더의 성능 향상을 위해 다중 참조 프레임 기법과 묵시적 가중 예측 기법을 이용하고 낮은 외부 메모리 접근율을 위해 이전 참조 프레임 데이터를 재사용하는 인터 예측기 하드웨어 구조를 제안한다. 참조 소프트웨어JM16.0과 비교하여 참조 프레임 접근율이 약 24%만큼 감소하고 참조 영역 메모리가 약 46%만큼 감소하였다. 통합 구조는 Verilog HDL로 설계되고 Magnachip 0.18um공정으로 합성한 결과 게이트 수는 약 2,061k 이고 91Mhz로 동작한다.

A Clock and Data Recovery Circuit with Adaptive Loop Bandwidth Calibration and Idle Power Saved Frequency Acquisition

  • Lee, Won-Young;Jung, Chae Young;Cho, Ara
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권4호
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    • pp.568-576
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    • 2017
  • This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

Optimal Bandwidth Allocation and QoS-adaptive Control Co-design for Networked Control Systems

  • Ji, Kun;Kim, Won-Jong
    • International Journal of Control, Automation, and Systems
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    • 제6권4호
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    • pp.596-606
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    • 2008
  • In this paper, we present a co-design methodology of dynamic optimal network-bandwidth allocation (ONBA) and adaptive control for networked control systems (NCSs) to optimize overall control performance and reduce total network-bandwidth usage. The proposed dynamic co-design strategy integrates adaptive feedback control with real-time scheduling. As part of this co-design methodology, a "closed-loop" ONBA algorithm for NCSs with communication constraints is presented. Network-bandwidth is dynamically assigned to each control loop according to the quality of performance (QoP) information of each control loop. As another part of the co-design methodology, a network quality of service (QoS)-adaptive control design approach is also presented. The idea is based on calculating new control values with reference to the network QoS parameters such as time delays and packet losses measured online. Simulation results show that this co-design approach significantly improves overall control performance and utilizes less bandwidth compared to static strategies.

Method of Measuring the Occupied Bandwidth of IS-95 Base Station at Remote Site

  • Lim, Jong-Soo;Kim, Sang-Tae
    • Journal of electromagnetic engineering and science
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    • 제3권1호
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    • pp.7-11
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    • 2003
  • CDMA(code division multiple access) has very large peak to average power ratio(PAR) and behave as noise-like wide band digital signals with 1.2288 Mbps transmission rate. For signals with high PAR like CDMA, it is reasonable to prescribe occupied bandwidth(OBW) as average occupied bandwidth. Bandwidth measurements of CDMA signals at remote site are affected by co-channel and adjacent channel interference from adjacent CDMA base station, distortion of signal by fading effect, spurious emission and environment noises. In this study, we have compared OBW measurements in an on-air environment with those measured in a base station using adjacent channel leakage ratio(ACLR) as a reference measurement factor. As results of analysis, the OBW at ACLR$\geq$35 ㏈ shows nearly same statistical characteristics regardless of the measurement locations and environments.

화상회의 시스템을 위한 대역폭 관리 알고리즘 설계 및 구현 (Design and Implementation of Bandwidth Management Algorithm for Video Conference System)

  • 구명모;정상운;김상복
    • 한국멀티미디어학회논문지
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    • 제3권4호
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    • pp.399-406
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    • 2000
  • 다자간 화상회의에서 발생하는 네트워크 혼잡상태에 동적으로 적응하기 위한 연구로는 송신자기반기법과 수신자기반 기법이 있는데, 전자는 수신자들의 평균 손실률에 따른 전송률로 가용 대역폭이 높은 수신자의 대역폭 낭비가 발생하며, 후자는 수신자들의 가용 대역폭에 따른 레이어(layer)를 동적으로 나누는 방법이 부족하다. 이를 위해 본 논문에서는 수신자의 네트워크 상태에 따라 정상상태와 혼잡상태로 구분하는 두 개의 멀티캐스트 그룹을 형성하고, 수신자가 손실률에 따라 동적으로 그룹을 선택함으로써 대역폭에 적합한 품질의 서비스를 받을 수 있도록 하는 대역폭 관리 알고리즘을 설계한 후 이를 구현하였다. 실험을 통한 결과를 살펴볼 때 수신자는 손실률에 따라 적합한 그룹을 선택함으로써 대역폭 낭비가 발생하는 문제점을 개선할 수 있었다.

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