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http://dx.doi.org/10.6109/jkiice.2012.16.12.2725

Design of a Low Memory Bandwidth Inter Predictor Using Implicit Weighted Prediction Technique  

Kim, Jinyoung (한밭대학교 정보통신전문대학원)
Ryoo, Kwangki (한밭대학교 정보통신공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.16, no.12, 2012 , pp. 2725-2730 More about this Journal
Abstract
In this paper, for improving the H.264/AVC hardware performance, we propose an inter predictor hardware design using a multi reference frame selector and an implicit weighted predictor. previous reference frame are reused for Low Memory Bandwidth. The size of the reference memory in the predictor was reduced by about 46% and the external memory access rate was reduced by about 24% compared with the one in the reference software JM16.0. We designed the proposed system with Verilog-HDL and synthesized inter predictor circuit using the Magnachip 0.18um CMOS standard cell library. The synthesis result shows that the gate count is about 2,061k and the design can run at 91MHz.
Keywords
H.264/AVC; inter predictor; reference frame; weighted prediction;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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