• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.719-725
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• 1986

Reed-solomon(R-S) code is very effective to coerrect both random and burst errors over a noise communication channel. However, the required hardware is very complex if the B/M algorithm was employed. Moreover, when the error correction system consists of two R-S decoder and de-interleave, the I/O data bns lines becomes 9bits because of an erasure flag bit. Thus, it increases the complexity of hardware. This paper describes the R-S decoder which consisits of a error correction section that uses a direct decoding algorithm and erasure generation section and a erasure generation section which does not use the erasure flag bit. It can be shown that the proposed R-S dicoder is very effective in reducing the size of required hardware for error correction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.882-885
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• 2010

In view of the severe energy constraint in sensor networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented FEC (Forward Error Correcting) codes in terms of their power consumption. One method of FEC is RS (Reed-Solomon) coding, which uses block codes. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 138, 132, 126, 111, and 103 respectively.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.103-106
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• 2004

본 논문에서는 PC 기반 지상파 DMB(Terrestrial Digital Multimedia Broadcasting, T-DMB) 수신기를 위한 SW 최적화에 대해 설명한다. 이 수신기는 PC 외부에 지상파 DMB 신호를 안테나로 수신하여 복조하고 채널 복호하는 프론트 엔드(front-end) 수신 모듈을 이용, USB를 통하여 RS(Reed-Solomon) 부호화된 MPEG-2 TS(Transport Stream) 데이터를 읽어 들여 RS 복호, TS 역다중화, 비디오 복호, 오디오 복호 등의 SW 처리 과정을 거쳐 디스플레이 상에 수신 내용을 표시하게 된다. 본 논문에서는 저사양 PC에서도 T-DMB를 수신할 수 있도록 H.264/MPEG-4 AVC(Advanced Video Coding) 복호 과정을 최적화한 결과에 대해 설명한다.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.2
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• pp.195-199
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• 2010

(255,223) RS(Reed-Solomon) code which is the CCSDS(Consultative Committee for Space Data Systems) standard was used in the STSAT-3 to correct errors during the downlink of payload data. The RS encoder developed by VHDL was implemented in MMU(Mass Memory Unit). Moreover, the RS decoder developed by C-language was implemented in the DRS(Data Receiving System) of ground station. In this paper, we reported the design and analysis results of RS(255,223) for STSAT-3. The BER(Bit Error Rate) performance from MMU to DRS was confirmed through the downlink test at 16 Mbps. Also, the error correction performance and capability of RS(255,223) was tested by the manual attenuation of the RF(Radio Frequency) signal in the X-band transmitter resulting in putting some errors in the communication line.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.83-90
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• 2010

In wireless sensor networks, the data transmitted from the sensor nodes are susceptible to corruption by errors which caused of noisy channels and other factors. In view of the severe energy constraint in Sensor Networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented RS (Reed-Solomon) codes in terms of their BER performance and power consumption. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. The results of experiment validate the performance of proposed method to provide high degree of reliability in low-power communication. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 173.7, 169.1, 163.9, 150.7, and 149.7 respectively. The evaluation based on packet reception ratio (PRR) indicates that the RS(255,239) extends a sensor node's communication range by up about 3 miters.