• Title/Summary/Keyword: Redundant Path

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An Efficient Overlay for Unstructured P2P File Sharing over MANET using Underlying Cluster-based Routing

  • Shah, Nadir;Qian, Depei
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.5
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    • pp.799-818
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    • 2010
  • In traditional unstructured P2P file sharing network, each peer establishes connections with a certain number of randomly chosen other peers. This would lead to redundant traffic and P2P network partition in mobile ad hoc network (MANET). We propose an approach to construct an efficient unstructured P2P overlay over MANET using underlying cluster-based routing (CBRP). One of the peers in the P2P network is used as a root-peer to connect all peers. Each peer maintains connection with physically closer peers such that it can reach the root-peer. The peer constructs a minimum-spanning tree consisting of itself, its directly connected neighbor peers and 2-hop away neighbor peers to remove far away redundant links and to build an overlay closer to the physical network. Due to on-demand nature of inter-cluster routing of CBRP, the positioning algorithm for MANET is used to retrieve the file by a peer from the source peer via shorter path in the physical network. We can show by simulation that our approach performs better in comparison with the existing approach.

A Pre-Resource Reservation Mechanism using NSIS protocol (NSIS 프로토콜을 이용한 사전자원예약 방안)

  • Kim, Sun-Young;Byun, Hae-Sun;Lee, Mee-Jeong
    • Journal of KIISE:Information Networking
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    • v.35 no.6
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    • pp.538-548
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    • 2008
  • In the Internet Engineering Task Force(IETF), Next Step in Signaling(NSIS) working group, proposed a mechanism to discover the Crossover Node(CRN), when the route is changed by Mobile Node(MN) handover. The CRN is divergence or convergence node on old and new path for reserving resources. Trough the CRN discovery mechanism, it possible to reduce a signaling delay and avoid the redundant reservation on the common path between old and new path. However, the QoS(Quality of Service) can be guaranteed continuously while the MN is performing handover, it is needed to pre-reserve the resource on the new path before completion of the handover. When the nodes on the new path try to make a pre-resource reservation before the handover, it is difficult to pre-reserve the resource with the existing CRN discovery mechanism. Therefore, we proposed a Passive CRN(PCRN) discovery scheme and pre-resource reservation mechanism. The PCRN which means an initial common point between the current reserved and the new paths, where the handover can take place.

Storage and Retrieval of XML Documents Without Redundant Path Information (경로정보의 중복을 제거한 XML 문서의 저장 및 질의처리 기법)

  • Lee Hiye-Ja;Jeong Byeong-Soo;Kim Dae-Ho;Lee Young-Koo
    • The KIPS Transactions:PartD
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    • v.12D no.5 s.101
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    • pp.663-672
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    • 2005
  • This Paper Proposes an approach that removes the redundancy of Path information and uses an inverted index, as an efficient way to store a large volume of XML documents and to retrieve wanted information from there. An XML document is decomposed into nodes based on its tree structure, and stored in relational tables according to the node type, with path information from the root to each node. The existing methods using path information store data for all element paths, which cause retrieval performance to be decreased with increased data volume. Our approach stores only data for leaf element path excluding internal element paths. As the inverted index is made by the leaf element path only, the number of posting lists by key words become smaller than those of the existing methods. For the storage and retrieval of U data, our approach doesn't require the XML schema information of XML documents and any extension of relational database. We demonstrate the better performance of on approach than the existing approaches within the scope of our experiment.

QoS-guaranteed Routing for Wireless Sensor Networks (무선 센서 네트워크를 위한 QoS 보장 라우팅)

  • Heo, Jun-Young
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.11 no.6
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    • pp.23-29
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    • 2011
  • In some applications of wireless sensor networks, requirements such as energy efficiency, real-time, and reliable delivery need to be considered. In this paper, we propose a novel routing algorithm for wireless sensor networks. It provides real-time, reliable delivery of a packet, while considering energy awareness. In the proposed algorithm, a node estimates the energy cost, delay and reliability of a path to the sink node, based only on information from neighboring nodes. Then, it calculates the probability of selecting a path, using the estimates. When packet forwarding is required, it randomly selects the next node. A path with lower energy cost is likely to be selected, because the probability is inversely proportional to the energy cost to the sink node. To achieve real-time delivery, only paths that may deliver a packet in time are selected. To achieve reliability, it may send a redundant packet via an alternate path, but only if it is a source of a packet. Experimental results show that the proposed algorithm is suitable for providing energy efficient, real-time, reliable communications.

A Design of Pipelined Adaptive Decision-Feedback Equalized using Delayed LMS and Redundant Binary Complex Filter Structure (Delayed LMS와 Redundant Binary 복소수 필터구조를 이용한 파이프라인 적응 결정귀환 등화기 설계)

  • An, Byung-Gyu;Lee, Jong-Nam;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.60-69
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

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Improvement Strategy of System Unavailability by Review of Logical Structure and Reliability Importance of Reliability Block Diagram (RED) and Fault Tree Analysis (FTA) (RBD와 FTA의 논리구조와 신뢰성 중요도의 고찰에 의한 시스템 비시간가동률 개선방안)

  • Choi, Sung-Woon
    • Journal of the Korea Safety Management & Science
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    • v.13 no.3
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    • pp.45-53
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    • 2011
  • The research proposes seven elimination rules of redundant gates and blocks in Fault Tree Analysis (FTA) and Reliability Block Diagram (RBD). The computational complexity of cut sets and path sets is NP-hard. In order to reduce the complexity of Minimal Cut Set (MCS) and Minimal Path Set (MPS), the paper classifies generation algorithms. Moreover, the study develops six implementation steps which reflect structural importance (SI) and reliability importance (RI) from Reliability Centered Maintenance (RCM) that a priority of using the functional logic among components is to reduce (improve) the system unavailability (or availability). The proposed steps include efficient generation of state structure function by Rare Event Enumeration (REA). Effective use of importance measures, such as SI and ill measures, is presented based on the number and the size of MCS and MPS which is generated from the reference[5] of this paper. In addition, numerical examples are presented for practitioners to obtain the comprehensive understanding of six steps that is proposed in this research.

Autonomous Network Combination of RAID System to read/write Performance Improvement (RAID 시스템에서 자율적 네트웍 조합에 의한 읽기/쓰기 성능 개선)

  • 최귀열
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.1
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    • pp.158-163
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    • 2003
  • When the number of disks array systems that contain multiple disk drives, system performance is limited by a bottleneck at a centralized controller at a communication path than uses a bus. A redundant array of inexpensive disks(RAID) consists of many disks to enable high performance and large capacity. We evaluate a scalable architecture called Autonomous network, in which the controller functions are distributed to all disk drives and each disk has autonomy in processing its tasks. Disks drives enable better scalability and more effective utilization of system resources than with a hierarchical system. Autonomous network provided high read/write performance throughput in proportion to the number of disks.

Dual Edge-Triggered NAND-Keeper Flip-Flop for High-Performance VLSI

  • Kim, Jae-Il;Kong, Bai-Sun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.2
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    • pp.102-106
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    • 2003
  • This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

The Implementation of Communication Protocol for Semiconductor Equipments using Directed Diffusion (직접 확산 방식을 이용한 반도체 장비 통신 프로토콜 구현)

  • Kim, Doo Yong;Cho, Hyun Chan
    • Journal of the Semiconductor & Display Technology
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    • v.12 no.2
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    • pp.39-43
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    • 2013
  • The semiconductor equipments generate necessary data through communication networks for the effective manufacturing processes and automation of semiconductor equipments. For transferring data between semiconductor equipments and sending data to monitor equipments, several standards for communication protocols have been proposed. Communication networks in semiconductor manufacturing systems will transmit a lot of data traffic, which can be vulnerable in data delay and network failure. Therefore, it is required that data traffic need to be distributed. To accomplish this objective, we recommend the use of a redundant and valuable communication path which is constructed by a wireless sensor network. In this paper, the directed diffusion method for wireless sensor networking is suggested for networking semiconductor equipments. It is shown that how the directed diffusion is employed to connect semiconductor equipments. Also, we show how to implement the SECS of semiconductor equipments communication protocols based on the directed diffusion.

RB 복소수 필터구조와 DLMS 알고리듬을 이용한 Pipelined ADFE의 설계

  • 안병규;신경욱
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.11a
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    • pp.534-537
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    • 1999
  • This paper describes a design of pipelined adaptive decision-feedback equalizer (PADFE) for high bit-rate wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of ADFE by using delayed least-mean-square (DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of ADFE including filter laps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters (filter tap, coefficient and internal bit-width, etc.) and equalization performance (bit error rate, convergence speed, etc.) are analyzed by algorithm-level simulation using COSSAP. The PADFE was designed using VHDL and Synopsys, and mapped into two ALTERA FLEX10k100 FPGAs.

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