• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.5
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• pp.560-566
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• 2003

Recently, many researches on RC(Reconfigurable Computing) with highly complex FPGA's and reconfigurable processors have been reported, and even some attempts for commercialization have been successful. In this paper, we introduce the design methodology for implementing DES crypto algorithm on small-capacity FPGA by using its dynamic reconfigurability and a system-level verification technique. Throughout this design project, we could evaluate the effectiveness of this approach, which is the dynamic reconfigurability of FPGAs makes the efficient trade-off between the performance and the cost robustly viable.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.3
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• pp.339-348
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• 2011

Reconfigurable manufacturing system (RMS), alternatively called changeable manufacturing, is a new manufacturing paradigm designed for rapid change in hardware and software components in order to quickly adjust production capacity and functionality in response to sudden changes in market or in regulatory requirements. Although there has been much progress in hardware components during the last decade, not much work has been done on operational issues of RMS. As one of starting studies on the operational issues, we suggest a framework for the system setup and scheduling problems to cope with the reconfigurability of RMS. System setup, which includes batching, part grouping, and loading, are concerned with the pre-arrangement of parts and tools before the system begins to process, and scheduling is the problem of allocating manufacturing resources over time to perform the operations specified by system setup. The framework consists of 8 scenarios classified by three major factors: order arrival process, part selection process, and tool magazine capacity. Each of the scenarios is explained with its subproblems and their interrelationships.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.6
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• pp.637-645
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• 2014

This paper presents a new $4{\times}4$ multi-port amplifier(MPA) structure using reconfigurable switching matrices as input and output hybrid matrices(IHM, OHM), and phase/amplitude error calibration circuits. According to the mode selection of the switches, output power can be flexibly and effectively managed since the number of PA's to be used and the number of output port to distribute/combine amplified signals can be controlled. In addition, the proposed structure contains the phase and amplitude error calibration block that helps produce identical amplitudes and desired phase differences to the $4{\times}4$ OHM, resulting in optimizing the port-to-port isolation of the MPA system.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.317-336
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• 2006

• Journal of the korean Society of Automotive Engineers
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• v.24 no.4
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• pp.32-36
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• 2002

• Journal of the Korean Society for Precision Engineering
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• v.29 no.4
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• pp.357-366
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• 2012

To schedule a Reconfigurable Manufacturing Cell (RMC), reconfiguration and setting decisions should be made first. Those decisions, together with characteristics of production orders, affect attainable performance of a system. So an integrative approach is required considering all decisions and characteristics rather than dealing with each of them separately. Pallet-fixture allocation, as a decision problem in setting, which determines the number of pallets to be equipped with each fixture type to produce different types of products, has rarely been investigated. In this study, several pallet-fixture allocation rules are proposed including both simple and novel ones. Then system performance is investigated through various combinations of setting and scheduling decisions (rules) for given system configurations and production orders, via simulation. The result shows that one of proposed pallet-fixture allocation rules which considers both configuration and order characteristic outperforms the others, justifying the necessity of an integrative approach in the RMC operation.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.4
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• pp.305-309
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• 2011

A sparse reconfigurable adaptive filter (SRAF) based on a photonic switch determines the appropriate time delays and weight values for an optical switch implementation of tapped-delay-line (TDL) systems. It is well known that the choice of switch delays is significantly important for efficiently implementing the SRAF. If the same values exist as calculating the sum of weight magnitudes for implementing the connection constraint required by the SRAF, conventional connection algorithm based on sequentially selection the maximum elements might not work perfectly. In an effort to increase the effectiveness of system identification, an upgraded connection algorithm used progressive calculation to obtain the better solution is considered in this paper. The performance of the proposed connection constraint algorithm is illustrated by computer simulation for a system identification application.