• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2944-2946
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• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.232-237
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• 2007

임베디드 시스템은 특정 목적을 수행하기 위해 설계된 시스템이며, 임베디드 운영체제는 실시간 운영체제 범용 운영체제로 나뉜다, 실시간 운영체제는 각 운영체제에서 각각의 API를 제공하기 때문에 응용프로그램 작성 시 API를 새로 익혀야 되는 단점이 있다. 범용 운영체제는 사용자에게 익숙한 POSIX API를 제공 하지만 커널 이미지 크기가 커서 센서와 같은 메모리가 작은 운영체제에는 이식하지 못하는 단점이 있다. 본 논문에서는 이러한 단점을 보안하고 장점을 살리기 위해 컨포넌트화 하여 확장 및 재구성이 가능하도록 하고 POSIX 기반의 API를 제공하여 응용 프로그램 작성에 용의하도록 하는 KHIX 임베디드 시스템 운영체제를 설계 및 구현하고 고성능의 PXA255, 저성능의 ATmega128에 이식한 내용을 다룬다.

• Journal of the Korea Society of Computer and Information
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• v.14 no.7
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• pp.65-72
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• 2009

This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.656-658
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• 2013

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of an elliptic curve crypto-engine server farm. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.494-499
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• 2008

In this study, a Software Defined Radio(SDR) technology-based digital filtering technique applicable to a multiple channel processing system such as a wireless mobile communication system using Code Division Multiple Access(CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response(FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter(BPF) to reconfigure another system. The feasibility of the algorithm is verified by implementing a multiple channel signal generator that is reconfigurable to other system profiles, including those for a CDMA system and a WCDMA system on identical hardware platform.

• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.281-288
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• 2005

Efficient utilization of processing resources in a large multicomputer system with the possibility of fault occurrence depends on the reliable processor management scheme. This paper presents a dynamic and reliable processor allocation strategy to increase the performance of mesh-connected parallel systems with faulty processors The basic idea is to reconfigure a faulty mesh system into a maximum convex system using the fault-free upper or lower boundary nodes to compensate for the non-boundary faulty nodes. To utilize the non-rectangular shaped system parts, our strategy tries to allocate L-shaped submeshes instead of signaling the allocation failure. Extensive simulations show that the strategy performs more efficiently than other strategies in terms of the job response time md the system utilization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.212-218
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• 2012

A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.4
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• pp.386-394
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• 2012

Recent trends in the flexible manufacturing systems are morphing cell control for the shop-wide production operation system and providing the integrated operation and execution system together with vendor-specific FMC/FMS platform. In these requirements, the shop-floor level operation system plays a role of coordinating the control activity of each cell, and has to provide flexibility for the complexity of mixed operations of various cells. This paper suggests a system architecture for the mixed environments of multi-cells and job shop, its corresponding enabling technologies based on comparative studies with other related studies and commercialized systems. This approach includes a process definition model considering the integration with upper BOM-BOP and external service modules, and reconfigurable device-level interface which provides dynamic interconnections with machine tools and cell controllers. The function modules and their implementation results are also described to provide the feasibility of the proposed approaches as the flexible shop-floor operation system for the multi-cell environments.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.6
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• pp.539-545
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• 2011

This paper describes an intelligent service robot system for managing a store in an unmanned environment. The robot can be a good replacement for humans because it is possible to work all day and to remember lots of information. We design a system architecture for configuring many intelligent functions of intelligent service robot system which consists of four layers; a User Interaction Layer, a Behavior Scheduling Layer, a Intelligent Module Layer, and a Hardware Layer. We develop an intelligent service robot 'Part Timer' based on the designed system architecture. The 'Part Timer' has many intelligent function modules such as face detection-recognition-tracking module, speech recognition module, navigation module, manipulator module, appliance control module, etc. The 'Part Timer' is possible to answer the phone and this function gives convenient interface to users.