• 한국통신학회논문지
• /
• 제33권9A호
• /
• pp.900-908
• /
• 2008

This paper presents the implementation and performance test of a Digital IF transceiver for a SDR-based mobile communication base station. The transceiver is reconfigurable to HSDPA and to three profiles, 7 MHz, 3.5 MHz, and 1.75 MHz, each incorporating the IEEE 802.16d WiMAX standard. The transceiver can be reconfigured to other standard profiles through software downloaded onto identical hardware platforms. Experimental results show that the transceiver can be reconfigured to other systems and the performance of the transceiver satisfies the recommended performance criteria of each standard.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2019년도 전력전자학술대회
• /
• pp.142-144
• /
• 2019

Nowadays, multi-MHz wireless power transfer (WPT) system has received a great concern of study due to its desirable characteristics such as user convenience, system compact and better safety as compared to the conventional DC-DC with cord. This paper presents a solution for WPT Lithium Batteries charger with Constant Current (CC) and Constant Voltage (CV) charging process. The proposed system consists of a high frequency class D power amplifier, a pair of PCB coil, transformable high-order resonant network and a full-bridge rectifier. The charger can be implemented CC /CV charging profile thanks to automatic reconfigurable resonant compensator. Therefore, the battery can be fully charged without the help of an additional DC/DC converter. The simulation and 50W-6.78-MHz hardware experimental results are presented to verify the feasibility of the proposed method and to evaluate the performance of the proposed wireless battery charger.

• 한국생산제조학회지
• /
• 제8권5호
• /
• pp.54-62
• /
• 1999

This paper describes the design and implementation of a PC(personal computer) based open architecture machine tool controller. The hardware of open architecture CNC has generally a motion control board on a PC for controlling a servo motor. But this paper describes open architecture hardware that consists of a PC, a counter board a DAC board and a DIO board only. This makes it easy to generate CNC software module in a hardware-independent way. The proposed open architecture CNC software runs on the MS-Windows NT. The paper describes a method of con-trolling servo motors using a real-time timer of MS-Windows NT and a commercial real-time operating system on the MS-Windows. NT. An open and reconfigurable software module is made up of an object and an API(application programming interface). Using the object and the API a new CNC system can be quickly configured to control dif-ferent machine tools. The proposed open architecture CNC system is applied to 4-axis lettering center.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.452-455
• /
• 1999

We introduce an evolutionary approach to on-line learning for mobile robot control using reconfigurable hardware. We use genetic programming as an evolutionary engine. Control programs are encoded in tree structure. Genetic operators, such as node mutation, adapt the program trees based on a set of training cases. This paper discusses the advantages and constraints of the evolvable hardware approach to robot learning and describes a FPGA implementation of the presented genetic programming method.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 하계학술대회 논문집 G
• /
• pp.2944-2946
• /
• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• 대한전자공학회논문지SD
• /
• 제41권5호
• /
• pp.61-70
• /
• 2004

뉴럴 네트워크는 동작 모드를 학습과 인지 과정으로 구분할 수 있다. 학습은 다양한 입력 패턴에 대하여 학습자가 원하는 결과값을 얻을 때까지 결합계수를 업데이트하는 과정이고, 인지는 학습을 통해 결정된 결합계수와 입력 패턴과의 연산을 수행하는 과정이다. 기존의 내적연산 프로세서는 처리 속도를 개선하고 하드웨어 복잡도를 줄이는 다양한 구조가 연구되었지만 뉴럴 네트워크의 학습과 인지모드에 대한 차별화된 구조는 없었다. 이를 위해, 본 논문에서는 재구성 가능한 뉴럴 네트워크 구현을 위한 새로운 저전력 내적연산 프로세서 구조를 제안한다. 제안한 구조는 학습모드에서 기존의 비트-시리얼 내적연산 프로세서와 같이 동작을 하여, 비트-레벨의 타른 처리 및 하드웨어 구현에 적합하고 높은 수준의 파이프라인 적용이 가능하다는 장점을 가진다. 또한, 인지모드에서는 고정된 결합계수에 따라 연산을 수행할 활성화 유닛을 최소화시킴으로서 전력 소비를 줄일 수 있다. 시뮬레이션 결과 활성화 유닛은 결합계수에 의존적이기는 하지만 50% 내외까지 줄일 수 있음을 확인하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -2
• /
• pp.924-927
• /
• 2002

In this paper we proposed the design space exploration environment of re-configurable hybrid systems and evaluate the performance by changing design parameters. With this, we analyzed the effect of various scheduling methods which determine how we allocate hardware/software resources to application program. A simple static (fixed) mapping strategy produces almost the same performance compared with a sophisticated dynamic mapping strategy especially when a CPU is already busy with its pre-assigned own tasks.

• 전기학회논문지
• /
• 제58권10호
• /
• pp.2059-2063
• /
• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Journal of information and communication convergence engineering
• /
• 제6권4호
• /
• pp.376-382
• /
• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Smart Structures and Systems
• /
• 제3권1호
• /
• pp.69-88
• /
• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.