• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.151-158
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• 2007

Quadtree, which is a hierarchical data structure, is a very important data structure to represent images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The computation of block location is one of important geometry operations in image processing, which extracts a component completely including a given block. In this paper, we present a constant time algorithm to compute the block location of images represented by quadtrees, using three-dimensional $n\times n\times n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to deal with the locational codes of quardtree on the hierarchical structure of $n\times n\times n$ RMESH.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.207-214
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• 2003

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The linear translation is one of important operations in image processing, which moves the image by a given distance. In this paper, we present an algorithm to perform the linear translation of binary images represented by quadtrees, using three-dimensional $n{\times}n{\times}n$ processors on RMESH (Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of n${\times}$n${\times}$n RMESH.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1170-1174
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• 2009

Two frequency-reconfigurable antennas have been designed and combined in a space with limited volume, i.e., 40mm ${\times}$ 20mm ${\times}$ 6mm. Each antenna can be reconfigured to operate at different frequency bands depending on the state of an embedded switch, which is implemented using a PIN diode. The first antenna can be switched between 0.82GHz ${\sim}$ 0.96GHz band (GSM/ CDMA) and 1.7GHz ${\sim}$ 2.17GHz band (DCS/ PCS/ WCDMA), which are cellular bands. The second antenna can be switched between 3.4GHz ${\sim}$ 3.6GHz band (mWiMax) and 2.3GHz ${\sim}$ 2.5GHz, 5.15GHz ${\sim}$ 5.35GHz bands (WiBro/ WLAN 11a/b/g/n), which are connectivity bands. The proposed combined antenna operates both over cellular bands and connectivity bands concurrently. The choice of the operation bands is made independently by the states of the two switches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1177-1180
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• 2005

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.664-665
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• 2013

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• ETRI Journal
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• v.39 no.5
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.110-116
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• 2012

This paper proposes a new diversity antenna which is the base of MIMO, tunable and reconfigurable antennas. The antenna has a small size and high inter-antenna isolation resulting from the compact radiating element comprising a meandered line and an open-loop combined in one limited uniplanar space and a modified T-shaped decoupling structure, respectively. In a WiMAX band, the radiating element and the entire antenna are $0.092{\lambda}$ and $0.2216{\lambda}$ in size, which shows effective size-reduction and the gain and efficiency of the proposed antenna attached to the ground of a handheld device are 3.7dBi and 56% acceptable to the industrial standard.

• ETRI Journal
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• v.31 no.5
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• pp.545-553
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• 2009

String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on-chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.117-122
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• 2006

In this paper, we present a simple and general soft bit decision expression for a Gray coded PAM signal over additive white Gaussian noise(AWGN) channel with the log likelihood ratio(LLR). In order to reduce the complexity of the LLR calculation, we make the bitwise LLR expression simple by replacing the mathematical max functions of the conventional Max-Log-MAP expression with simple arithmetic functions associated with some deterministic parameters, such as a received value and distance between symbols on a signal space. Taking the implementation issues, like the area of silicon, the power consumption, the timing latency, and so on, into consideration, we submit that the proposed method is a promising alternative way to conventional methods for reconfigurable systems.