• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Journal of the Korea Computer Industry Society
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• v.3 no.9
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• pp.1235-1244
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• 2002

This paper proposes a group key management protocol for a secure of all the multicast user in PIM-SM multicast group communication. With prosed architect, subgroups for multicast secure group management will be divided by RP (Rendezvous-Point) unit and each RP has a subgroup manager. Each subgroup manager gives a secure key to it's own transmitter md the transmitter compress the data with it's own secure key from the subgroup manager. Before the transmitter send the data to receiver, the transmitter prepare to encrypt a user's service by sending a encryption key to the receiver though the secure channel, after choking the user's validity through the secure channel. As the transmitter sending a data after then, the architecture is designed that the receiver will decode the received data with the transmitter's group key. As a result, the transmitting time is shortened because there is no need to data translation by group key on data sending and the data transmition is possible without new key distribution at path change to SPT (Shortest Path Tree) of the router characteristic. Additionally, the whole architecture size is samller than the other multicast secure architecture by using the conventional PIM-SIM routing structure without any additional equipment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.1
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• pp.268-278
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• 2017

In this paper, we propose two novel detection schemes with low-complexity based on the unified receiver architecture which minimizes a fundamental tradeoff at rate-energy region in SWIPT system. The proposed detection schemes are twofold: The two-stage detection scheme and Euclidean distance combination detection scheme. The two-stage detection scheme detects amplitude information of symbols from rectified signals for energy harvesting. In the sequel, it detects symbols based on phase information of baseband signals for information decoding. The Euclidean distance combination detection scheme detects symbols using linear positive-weighted sum of two metrics: Euclidean distance based on baseband signals for information decoding and Euclidean distance based on rectified signals for energy harvesting. For numerical results, we confirm that the proposed detection scheme can achieve better performance than the conventional scheme in terms of symbol error rate, symbol success rate-energy region and achievable rate-energy region.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.853-861
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• 2009

In this paper, we propose the architecture of a multi-band receiver which can receive X-band, Ku-band, K-band and Ka-band signals. For implementing this architecture, we designed a wideband and high power VCO with a buffer stage. In order that a buffer does not affect the characteristic of a oscillation in steady state condition, output impedance of a oscillation part and input impedance of a buffer are orthogonally crossed. The fabricated VCO meets the performance parameter of the multi-band receiver which has a $14.00{\sim}15.20\;GHz$ bandwidth with respect to the tuning voltage, $0.0{\sim}8.0\;V$, and output power of $12{\sim}13\;dBm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.444-450
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• 2004

In mobile communications environment, STBC-OFDM(Space Time Block Code-Orthogonal Frequency Division Multiplexing) system with transmit diversity obtains the MRRC(Maximal Ratio Receiver Combining) diversity gain in time-invariant channel between two received symbols. But in time-variant channel, due to the interference between received symbols, MRRC diversity gain cant be obtained. So, when the mobile device with transmit diversity moves in high speed, the scheme to reduce the performance degradation due to the interference is needed. In this paper, we propose the receiver architecture with advanced transmit diversity, which improves the performance of STBC-OFDM system. The proposed architecture obtains the diversity gain without the change of transmit bandwidth at the receiver with the interference canceller using ZF(Zero Forcing) algorithm. Simulation results show performance improvement as doppler shift is increasing.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.652-656
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• 2011

In this paper, a transmitter-based multipath processing and inter-channel interference (ICI) cancellation scheme for a ultra-wideband (UWB) spatial multiplexing (SM) multiple input multiple output (MIMO) system is presented. It consists of taps delayed lines and zero-forcing (ZF) filters in the transmitter and correlators in the receiver. For a UWB SM MIMO system with N transmit antennas, M receive antennas, and Q resolvable multipath components, the BER performance of a linear transmit ZF scheme is analyzed in a log-normal fading channel and also compared with that of a receiver-based ICI rejection approach. It is found that when M ${\leq}$ N, the transmit ZF processing approach outperforms the ZF receiver while making the mobile units low-cost and low-power.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.533-534
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• 2008

This paper presents a multi-phase ring VCO for low-cost, low-power GPS receiver. In the RF band used in GPS, L1 band is now in commercial-use and L2,L5 are predicting to be commercial-use soon. Thus Wide band PLL and Cost-effective IC solutions are required for future multi-band GPS receiver that received three types band at once. A new PLL architecture for multi-band GPS application is proposed. Ring VCO is even smaller than LC-VCO and a good alternative for low-cost solution. Proposed multi-phase ring VCO offers wide frequency range covering L1, L2, and L5 band, 20% reduction of area, 23% reduction of PLL power and can generate I/Q without extra I/Q generator.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.181-182
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• 2008

In this paper, an cost-effective system architecture is proposed to implement digital predistortion scheme for linearizing the PA amplifing TDD wideband signal. To make digital predistorted signal for compensating nonlinearity of PA, a dedicated ADC and a frequency-down converter are necessary. Proposed scheme is based on the TDD feature that the RF receiver frontend is idle state during the downlink signal processing time and utilize them to make the digital predistorted signal for PA.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.67-73
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• 2015

This paper presents a fully integrated 3 - 5 GHz IR-UWB(impulse radio ultra-wide band) RFIC for Location based system. The receiver architecture adopts the energy detection method and for high speed sampling, the equivalent time sampling technique using the integrated DLL(delay locked loop) and 4 bit ADC. The digitally synthesized UWB impulse generator with low power consumption is also designed. The designed IR-UWB RFIC is implemented on $0.18{\mu}m$ CMOS technology. The receiver's sensitivity is -85.7 dBm and the current consumption of receiver and transmitter is 32 mA and 25.5 mA respectively at 1.8 V supply.