• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.529-538
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• 1992

Recently, image signal processing techniques for HDTV signal have been drastically developed. This kind of skill improvement on signal processing need specific memory device for video signal. in this paper, data latch scheme which implements CMOS flip-flop to hold Information from in-put strobe and new reading method is devised to attain a proper access time suitable for HDTY signal. Compared with conventional write scheme, data latch method has two procedures to complete write operation : bit line write and storage cell write, enabling concurrent I /0 operation at the same address. Also, fast read access is possible through the method similar to static column mode and the separated read word line.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.1
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.1
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• pp.91-95
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. But NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, log-structured filesystem was proposed such as YAFFS. However, YAFFS sequentially retrieves an array of all block information to allocate free block for a write operation. Also before the write operation, YAFPS read the array of block information to find invalid block for erase. These could reduce the performance of the filesystem. This paper suggests fast operation method for NAND flash filesystem that solves the above-mentioned problems. We implemented the proposed methods in YAFFS. And we measured the performance compared with the original technique.

• Journal of Convergence for Information Technology
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• v.7 no.2
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• pp.59-65
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• 2017

In order to realize the operation of the creative modular toy, it is required to record the motion and to read and repeat the motion. At this time, a control potentiometer is used to read the absolute angle of rotation of the toy motion output shaft. However, the unstable part of the sensing area of the potentiometer is present in a certain region, which may lead to instability of the motor control. In this paper, we propose an algorithm to find the absolute angle of one rotation by reading two stable potentiometers on one axis and reading each stable region. We also describe the correction algorithm that is needed to perform multiple rotations. The proposed method is applied to Topobo modular toys to record the operation and perform iterative operation. In addition, multi-turn operation is recorded and operated to suggest the usefulness of the proposed method. In the future, we will expand the functions of recording and playback through various actions.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.1-7
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• 2012

In this paper, we design and implement the simulator for WAN storage replication model performance evaluation in cloud computing environment. Each cloud of simulator is composed of virtual machine emulator and storage emulator. The virtual machine emulator is composed of read/write ratio module, the read/write sequence combination module, and the read/write request module. The storage emulator is composed of storage management module, data transfer module, read/write operations module, and overhead processing module. Using the simulator, we evaluate performance of migration scheme, pre-copy and the post-copy, considering about read/write ratio, network delay, and network bandwidth. Through simulation, we have confirmed that the average migration time of pre-copy was decreased proportional to the read operation. However, average migration time of post-copy was on the increase. Also, the average migration time of post-copy was increased proportional to the network delay. However, average migration time of pre-copy was shown uniformly. Therefore, we show that pre-copy model more effective to reduce the average migration time than the post-copy model. The average migration time of pre-copy and post-copy were not affected by the change of network bandwidth. Therefore, these results show that selects the storage replication model to be, the network bandwidth know not being the important element.

• Proceedings of the Safety Management and Science Conference
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• 2007.04a
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• pp.27-33
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• 2007

There are many reason for unsafety action without safety operation. The reason is no standard safety operation in company or the workers never get a enough education. Standard safety operation is prepared by paper for accurate directions and orders and operators must read the paper to prevent an error of action. Also an essential particular is safety of equipment and machine must be assumed to establish standard safety operation then safety of operations will be possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.145-145
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• 2009

In this paper, we suggest how to adapt RFID system to train switching process, and then what we get the merit or problem. We analyze the train switching process to adapt RFID system on the process and have field test. The role of RFID system in train switching process is to automatically read car position information. The specification of the test system is 900MHz, and Gen2 passive tag. If we get the system which automatically read car position information in train switching yard, it prevents human errors and makes more reliability, the performance of train operation will grow up. Even though the environment of train switching yard is outdoors, the test result gives us the ability to adapt RFID system to train switching process and the process will be more simple.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.647-650
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• 2005

In this paper, a low voltage SRAM using double boosting scheme is described. A low supply voltage deteriorates the static noise margin (SNM) and the cell read-out current. For read/write operation, a selected word line and cell VDD bias are boosted in a different level using double boosting scheme. This increases not only the static noise margin but also the cell readout current at a low supply voltage. A low voltage SRAM with 32K ${\times}$ 8bit implemented in a 0.18um CMOS technology shows an access time of 26.1ns at 0.8V supply voltage.