• Journal of the Korean Society for Aviation and Aeronautics
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• v.8 no.1
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• pp.111-124
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• 2000

In this study, pilot's read-back errors were reviewed in terms of its cause and consequence while FAA tried to weigh a new initiative in the atc-pilot communication dispute in opposition of a majority of the aviation community by addressing an interpretive rule of 14CFR 91. Especially human factors in ATC communications were outlined with a view to suggest a line of recommendations for a successful accomplishment of safe flight in the busy terminal airspace.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.347-353
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• 2017

We present a STT-MRAM read-circuit which mitigates the performance degradation caused by offsets from device mismatches. In the circuit, a single current source supplies read-current to both the data and the reference cells sequentially eliminating potential mismatches. Furthermore, an offset-free pre-amplification using a capacitor storing the mismatch information is employed to lessen the effect of the comparator offset. The proposed circuit was implemented using a 130-nm CMOS technology and Monte Carlo simulations of the circuit demonstrate its effectiveness in suppressing the effect of device mismatch.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• The Journal of Fisheries Business Administration
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• v.38 no.1 s.73
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• pp.115-132
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• 2007

Implementing the automatic identification in supply chain management is essential for effective and efficient process control. Though the GTIN based bar code system is generally used as an automatic identification method in most industries, it can not identify individual item, and is not appropriated for products' reliability and safety management. So the RFID system with EPC is considered as a better solution for resolving those problems. This study reviewed automatic identification code systems and the attributes and characteristics of RFID Gen 2 which became a global standard recently for supply chain management. Particularly, this study analyzed RFID Gen 2 systems' read rates on various conditions including distances between tags and readers and between antennas, condensation, and several packing materials in practical supply chain environment. The results of this study showed that the RFID Gen 2 had high read ratio in practical application and would be adopted as a new automatic identification means for traceability systems.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.125-134
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• 1994

In real-time database systems, transactions's commitment done before the given deadlines is more important than just getting the maximum throughput. Transactions missing the given deadlines are no longer meaningful in real-time applications. Therefore, there is a need for new transaction processing models to meet the given deadlines in real-time database applications, because moat conventional transaction models are not designed to meet deadlines. In this paper we propose a new transaction models which uses multiple versions of a data item. The model uses read-from graphs and dynamic reorder of transactions to meet deadlines. A read-from graph contains the past read semantics of read operations and support the model to decide which database operation to be taken. Then, we show simulation results comparing the proposed model with other transaction models such as two phase locking model and the optimistic concurrency control model.

• Journal of the Optical Society of Korea
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• v.12 no.1
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• pp.52-56
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• 2008

An all-optical read only memory utilizing cross gain modulation in semiconductor optical amplifiers (SOAs) has been demonstrated for the first time to our knowledge. In our demonstration, an all-optical 2-to-4 line decoder constructed with SOAs has been employed for the construction of this all-optical read only memory. Storing four characters in an American standard code for information interchange (ASCII) format has been successfully carried out. Each character consisting of seven binary bits could be read out at a rate of 10 Giga characters per second.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1302-1305
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• 2006

We evaluated the usability of two kinds types of recently commercialized e-books through an analysis of their protocols, compared the time required to read an e-book with that for a paper book, and compared text display sizes that were easy to read for aged and young readers, under identical conditions. This showed clear problems with the usability of e-books for aged and young readers. It was found that it took longer for aged readers to read text in an e-book than for young readers, and that the size of text that aged readers found easy to read was different than for young readers.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.383-386
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• 2001

This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.05a
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• pp.44-47
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• 2018

시계열 데이터 처리를 위해 방대한 양의 데이터를 스토리지에서 빠르게 읽어와 처리하려는 움직임이 많아지고 있다. 이를 위해 스토리지의 read latency 를 개선하기 위한 여러 기법들이 제안되었지만, 이 기법들은 분산 노드의 스토리지 자원을 충분히 활용하지 못한다는 한계가 있다. 따라서 우리는 시계열 데이터를 실시간으로 처리하기 위해 스토리지에 병렬적으로 접근하여 read latency 를 개선하는 기법을 제안한다. 제안된 기법은 분산 환경에서 스토리지에 병렬적으로 접근하여, 각 노드에서 부분적으로 데이터를 읽어와 전체 데이터를 읽어오는 지연시간을 줄인다. 우리는 제안된 기법을 여러 노드로 구성된 분산 환경에서 구현하였다. 제안된 기법을 적용한 결과, 전체 데이터를 읽어오는 read latency 가 기존 기법보다 28.04% 줄어든 것을 확인하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.