• 제목/요약/키워드: Rapid thermal annealing process

검색결과 204건 처리시간 0.037초

고효율 태양전지의 저가화를 위한 Ni/Cu/Ag 전극의 Ni Silicide 형성에 관한 연구 (Investigation of Ni Silicide formation at Ni/Cu/Ag Contact for Low Cost of High Efficiency Solar Cell)

  • 김종민;조경연;이지훈;이수홍
    • 한국태양에너지학회:학술대회논문집
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    • 한국태양에너지학회 2009년도 춘계학술발표대회 논문집
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    • pp.230-234
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    • 2009
  • It is significant technique to increase competitiveness that solar cells have a high energy conversion efficiency and cost effectiveness. When making high efficiency crystalline Si solar cells, evaporated Ti/Pd/Ag contact system is widely used in order to reduce the electrical resistance of the contact fingers. However, the evaporation process is no applicable to mass production because high vacuum is needed. Furthermore, those metals are too expensive to be applied for terrestrial applications. Ni/Cu/Ag contact system of silicon solar cells offers a relatively inexpensive method of making electrical contact. Ni silicide formation is one of the indispensable techniques for Ni/Cu/Ag contact sytem. Ni was electroless plated on the front grid pattern, After Ni electroless plating, the cells were annealed by RTP(Rapid Thermal Process). Ni silicide(NiSi) has certain advantages over Ti silicide($TiSi_2$), lower temperature anneal, one step anneal, low resistivity, low silicon consumption, low film stress, absence of reaction between the annealing ambient. Ni/Cu/Ag metallization scheme is an important process in the direction of cost reduction for solar cells of high efficiency. In this article we shall report an investigation of rapid thermal silicidation of nickel on silngle crystalline silicon wafers in the annealing range of $350-390^{\circ}C$. The samples annealed at temperatures from 350 to $390^{\circ}C$ have been analyzed by SEM(Scanning Electron Microscopy).

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Blistering Induced Degradation of Thermal Stability Al2O3 Passivation Layer in Crystal Si Solar Cells

  • Li, Meng;Shin, Hong-Sik;Jeong, Kwang-Seok;Oh, Sung-Kwen;Lee, Horyeong;Han, Kyumin;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권1호
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    • pp.53-60
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    • 2014
  • Different kinds of post-deposition annealing (PDA) by a rapid thermal process (RTP) are used to enhance the field-effect passivation of $Al_2O_3$ film in crystal Si solar cells. To characterize the effects of PDA on $Al_2O_3$ and the interface, metal-insulator semiconductor (MIS) devices were fabricated. The effects of PDA were characterized as functions of RTP temperature from $400{\sim}700^{\circ}C$ and RTP time from 30~120 s. A high temperature PDA can retard the passivation of thin $Al_2O_3$ film in c-Si solar cells. PDA by RTP at $400^{\circ}C$ results in better passivation than a PDA at $400^{\circ}C$ in forming gas ($H_2$ 4% in $N_2$) for 30 minutes. A high thermal budget causes blistering on $Al_2O_3$ film, which degrades its thermal stability and effective lifetime. It is related to the film structure, deposition temperature, thickness of the film, and annealing temperature. RTP shows the possibility of being applied to the PDA of $Al_2O_3$ film. Optimal PDA conditions should be studied for specific $Al_2O_3$ films, considering blistering.

RF Magnetron Sputtering법으로 증착된 ZnNiO박막의 특성 (ZnNiO thin films deposited by r.f. magnetron sputtering method)

  • 오형택;이태경;김동우;박용주;박일우;김은규
    • 한국진공학회지
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    • 제12권4호
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    • pp.269-274
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    • 2003
  • The electrical, optical and structural properties of ZnNiO thin _ films deposited on Si substrates using rf-magnetron sputtering method have been investigated before and after the thermal annealing processes. The crystallinity of the ZnNiO thin film become degraded with increasing the Ni contents. This is mainly because the lattice of the thin film was expanded due to the oxygen-deficient conditions. Concerning the electrical properties of the thin film, the carrier concentration increases ($6.81\times10^{14}\textrm{cm}^{-2}$) and Hall mobility decreases (36.3 $\textrm{cm}^2$/Vㆍs) with higher doping concentration of Ni. However, the carrier concentration and Hall mobility became low ($1.10\times10^{14}\textrm{cm}^2$ and high (209.6 $\textrm{cm}^2$/Vㆍs), respectively, after the thermal annealing process at $1000 ^{\circ}C$. We also observed a strong luminescene center peaking at 546 nm in photoluminescence spectra, which was caused by a deep level center in the ZnO band gap with oxygen deficient ZnNiO structure.

새로운 저온 열처리 공정으로 제조된 SrBi2Ta2O9 박막의 결정성 및 전기적 특성 (The Crystallinity and Electrical Properties of SrBi2Ta2O9 Thin Films Fabricated by New Low Temperature Annealing)

  • 이관;최훈상;장유민;최인훈
    • 한국재료학회지
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    • 제12권5호
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    • pp.382-386
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    • 2002
  • We studied growth and characterization of $SrBi_2Ta_2O_9$ (SBT) thin films fabricated by low temperature process under vacuum and/or oxygen ambient. A metal organic decomposition (MOD) method based on a spin-on technique and annealing process using a rapid thermal annealing (RTA) method was used to prepare the SBT films. The crystallinity of a ferroelectric phase of SBT thin films is related to the oxygen partial pressure during RTA process. Under an oxygen partial pressure higher than 30 Torr, the crystallization temperature inducing the ferroelectric SBT phase can be lowered to $650^{\circ}C$. Those films annealed at $650^{\circ}C$ in vacuum and oxygen ambient showed good ferroelectric properties, that is, the memory window of 0.5~0.9 V at applied voltage of 3~7 V and the leakage current density of 1.80{\times}10^{-8}$ A/$\textrm{cm}^2$ at an applied voltage of 5V. In comparison with the SBT thin films prepared at 80$0^{\circ}C$ in $O_2$ ambient by furnace annealing process, the SBT thin films prepared at $650^{\circ}C$ in vacuum and oxygen ambient using the RTA process showed a good crystallization and electrical properties which would be able to apply to the virtul device fabrication precess.

$O_{2}$ re-annealing에 의한 식각된 PZT 박막의 식각 damage 개선 (Recovery of Etching Damage of the etched PZT Thin Films With $O_{2}$ Re-Annealing.)

  • 강명구;김경태;김창일;장의구;이병기
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
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    • pp.8-11
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    • 2001
  • In this study. the recovery of plasma induced damage in the etched PZT thin film with $O_2$ re-annealing have been investigated. The PZT thin films were etched as a function of $Cl_2/Ar$ and additive $CF_4$ into $Cl_{2}(80%)/Ar(20)%$. The etch rates of PZT thin films were $1600\dot{A}/min$ at $Cl_{2}(80%)/Ar(20)%$ gas mixing ratio and $1970\dot{A}/min$ at 30 % additive $CF_4$ into $Cl_{2}(80%)/Ar(20)%$. The etched profile of PZT films was obtained above 70 by SEM. In order to recovery properties of PZT thin films after etching, the etched PZT thin films were re-annealed at various temperatures in $O_2$ atmosphere. From the hysteresis curves, ferroelectrical properties are improved by $O_2$ re-annealing process. The improvement of ferroelectric behavior at annealed sample is consistent with the increase of the (100) and (200) PZT phase revealed by x-ray diffraction (XRD). From XPS analysis, intensity of Pb-O, Zr-O and Ti-O peak are increased and the chemical residue peak is reduced by $O_2$ re-annealing. The ferroelectric behavior consistent with the dielectric nature of TixOy is recovered by $O_2$ recombination during rapid thermal annealing process. From AFM images, it shows that the surface roughness of re-annealed sample after etching is improved.

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Fabrication and characterization of $WSi_2$ nanocrystals memory device with $SiO_2$ / $HfO_2$ / $Al_2O_3$ tunnel layer

  • Lee, Hyo-Jun;Lee, Dong-Uk;Kim, Eun-Kyu;Son, Jung-Woo;Cho, Won-Ju
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.134-134
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    • 2011
  • High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

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급속열처리를 통한 알루미나 나노템플릿의 기공 균일도 개선에 관한 연구 (A Study on Improved Pore Uniformity of Nano Template Using the Rapid Thermal Processor)

  • 김동희;김진광;권오대;양계준;이재형;임동건
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.637-638
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    • 2005
  • AAO templates were fabricated using a two-step anodization process with pretreatment such as electro polishing and annealing. To reduce process time and get well-aligned pore array, rapid thermal processor by an halogen lamp was employed in vacuum state at $500^{\circ}C$ for various time. The pore array of AAO template annealed at $500^{\circ}C$ for 2 h is comparable to a template annealed in conventional furnace at $500^{\circ}C$ for 30 h. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrierlayer thickness of 25 nm, and the pore depth of $9{\mu}m$. And the pore density can be as high as $2.0\times10^{10}cm^{-2}$.

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RTA 방법에 의해 Zn 도핑된 InP의 오믹저항 특성연구 (Study on Ohmic resistance of Zn-doping InP using RTA method)

  • 김효진;김인성;김태언;김상택;김선훈;기현철;이경민;양명학;고항주;김회종
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.237-238
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    • 2008
  • 본 연구에서는 APD 소자 제작시 주로 쓰이는 RTA에 의한 Zn 확산방법에 사용할 경우 undoped InP의 V/III비율에 따른 Zn원자의 확산, 도핑, 오믹저항의 성장을 조사하였다. RTA에 의한 확산 및 활성화 열처리 시 도핑 농도의 프로파일은 확산열처리만 한 경우보다 활성화 처리한 경우 더 커짐을 볼 수 있었다. SIMS 결과 활성화 처리 후 표면쪽에 Zn원자의 약간의 결핍현상을 보이는 데 이는 표면쪽에 Zn원자의 탈착이 약간 이루어지는 것으로 보인다. 이 원인은 결과적으로 오믹저항의 증가를 가져왔다.

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Electrical Properties of Sol-gel Derived Ferroelectric Bi3.35Sm0.65Ti3O12 Thin Films by Rapid Thermal Annealing

  • Cho, Tae-Jin;Kang, Dong-Kyun;Kim, Byong-Ho
    • Transactions on Electrical and Electronic Materials
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    • 제6권2호
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    • pp.51-56
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    • 2005
  • Ferroelectric Bi$_{3.35}$Sm$_{0.65}$Ti$_{3}$O$_{12}$(BSmT) thin films were synthesized using a sol-gel process. Bi(TMHD)$_{3}$, Sm$_{5}$(O$^{i}$Pr)13, Ti(O$^{i}$Pr)4 were used as the precursors, which were dissolved in 2­methoxyethanol. The BSmT thin films were deposited on Pt/TiO$_{x}$/SiO$_{2}$/Si substrates by spin­coating. The electrical properties of the thin films were enhanced using rapid thermal annealing process (RTA) at 600 $^{circ}$C for 1 min in O$_{2}$. Thereafter, the thin films were annealed from 600 to 720 $^{circ}$C in oxygen ambient for 1 hr, which was followed by post-annealed for 1 hr after depositing a Pt electrode to enhance the electrical properties. X-ray diffraction (XRD) and scanning electron microscopy (SEM) were used to analyze the crystallinity and surface morphology of layered perovskite phase, respectively. The remanent polarization value of the BSmT thin films annealed at 720 $^{circ}$C after the RTA treatment was 35.31 $\mu$C/cmz at an applied voltage of 5 V.

열처리방법에 따른 ${K_3}{Li_2}{Nb_5}{O_{15}}$(KLN)박막의 제작 (Preparation of ${K_3}{Li_2}{Nb_5}{O_{15}}$(KLN) Thin Films by Heat Treatment Methods)

  • 김광태;박명식;이동욱;조상희
    • 한국세라믹학회지
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    • 제37권8호
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    • pp.731-738
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    • 2000
  • KLN(K3Li2Nb5O15) has attracted a great deal of attention for their potential usefulness in piezoelectric, electro-optic, nonlinear optic, and pyroelectirc devices. Especially, the KLN single crystal has been studied in the field of optics and electronics. However it is hard to produce good quality single crystals due to the crack propagation during crystal growing. One of the solutions of this problem is prepartion of thin film. But the intensive study has not been conducted so far. In this study, after the KLN thin film were prepared by R.F. magnetron Sputtering method on SiO2/Si substrate, the post-annealing methods of RTA(rapid thermal annealin) and IPA(insitu post annealing) were employed. The deposition condition of KLN thin film was RF power(100 W), Working pressure(100 mtorr). The commonness of both RAT and IPA was that the higher were deposition and post annealing temperature, the higher was the intensity of XRD but the less surface roughness. The difference of post-annealing methods affected XRD phase and surface condition very much. And in IPA process, the influence of O2 had much effect on the formation of KLN phase.

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