• 한국결정성장학회지
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• 제7권2호
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• pp.309-314
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• 1997

Ag-Pd/$Al_2O_3$와 Pt 기판에 스핀온 방법으로 제조된 PZT 후막의 열처리 방법에 따른 전기적 특성을 조사하였다. 전기적 특성을 측정하기 위하여 상부전극으로 은(Ag)을 PZT표면에 충착하였다. 이렇게 만들어진 PZT 후막의 결정구조는 X-ray로 조사하였으며, 유전상수는 HP4284A를 사용하여 1 KHz, 10 mV에서 측정하였다. 또한 유전계수는 Berlincourt 피에조메터를 사용하여 측정하였다. 그 결과 3 wt% PbO가 첨가된 PZT 후막의 전기적 특성은 오히려 감소하였으며, Ag-Pd 전극은 Pt 전극을 대체할 수 있는 가능성이 매우 높았다. 특히 스핀온 방법으로 제조된 PZT 후막을 급속열처리(RTA)를 함으로써 전기적 특성을 크게 향상시킬 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Current Photovoltaic Research
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• 제3권3호
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• pp.75-79
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• 2015

Recently, $Cu_2ZnSn(S_xSe_{1-x})_4$ (CZTSSe) has been received a tremendous attraction as light absorber material in thin film solar cells (TFSCs), because of its earth abundance, inexpensive and non-toxic constituents and versatile material characteristics. Kesterite CZTSSe thin films were synthesized by sulfo-selenization of sputtered Cu/Sn/Zn stacked metallic precursors. The sulfo-selenization of Cu/Sn/Zn stacked metallic precursor thin films has been carried out in a graphite box using rapid thermal annealing (RTA) technique. Annealing process was done under sulfur and selenium vapor pressure using Ar gas at $520^{\circ}C$ for 10 min. The effect of tuning Se/(S+Se) precursor composition ratio on the properties of CZTSSe films has been investigated. The XRD, Raman, FE-SEM and XRF results indicate that the properties of sulfo-selenized CZTSSe thin films strongly depends on the Se/(S+Se) composition ratio. In particular, the CZTSSe TFSCs with Se/(S+Se) = 0.37 exhibits the best power conversion efficiency of 4.83% with $V_{oc}$ of 467 mV, $J_{sc}$ of $18.962mA/cm^2$ and FF of 54%. The systematic changes observed with increasing Se/(S+Se) ratio have been discussed in detail.

• Current Photovoltaic Research
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• 제3권4호
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• pp.135-139
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• 2015

$Cu_2SnS_3$ (CTS) based thin film solar cells (TFSCs) are of great interest because of its earth abundant, low-toxic and eco-friendly material with high optical absorption coefficient of $10^4cm^{-1}$. In this study, the DC sputtered precursor thin films have been sulfurized using rapid thermal annealing (RTA) system in the graphite box under Ar gas atmosphere for 10 minute. The systematic variation of sulfur powder during annealing process has been carried out and their effects on the structural, morphological and optical properties of CTS thin films have been investigated. The preliminary power conversion efficiency of 1.47% with a short circuit current density of $33.9mA/cm^2$, an open circuit voltage of 159.7 mV, and a fill factor of 27% were obtained for CTS thin film annealed with 0.05g of S powder, although the processing parameter s have not yet been optimized.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.458.2-458.2
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• 2014

We have demonstrated that simple brush-painted Ti-doped $In_2O_3$(TIO) films can be used as a cost effective transparent anodes for organic solar cells (OSCs). We examined the RTA effects on the electrical, optical, and structural properties of the brush painted TIO electrodes. By the direct brushing of TIO nanoparticle ink and rapid thermal annealing (RTA), we can simply obtain TIO electrodes with a low sheet resistance of 28.25 Ohm/square and a high optical transmittance of 85.48% under atmospheric ambient conditions. Furthermore, improvements in the connectivity of the TIO nano-particles in the top region during the RTA process play an important role in reducing the resistivity of the brush-painted TIO anode. In particular, the brush painted TIO films showed a much higher mobility ($33.4cm^2/V-s$) than that of previously reported solution-process transparent oxide films ($1{\sim}5cm^2/V-s$) due to the effects of the Ti dopant with higher Lewis acid strength (3.06) and the reduced contact resistance of TIO nanoparticles. The OSCs fabricated on the brush-painted TIO films exhibited cell-performance with an open circuit voltage (Voc) of 0.61 V, shot circuit current (Jsc) of $7.90mA/cm^2$, fill factor (FF) of 61%, and power conversion efficiency (PCE) of 2.94%. This indicates that brush-painted TIO film is a promising cost-effective transparent electrode for printing-based OSCs with its simple process and high performance.

• 한국재료학회지
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• 제17권4호
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• pp.207-214
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• 2007

We fabricated thermally-evaporated 10 -Ni/(poly)Si and 10 -Ni/1 -Ir/(poly)Si structures to investigate the microstructure of nickel monosilicide at the elevated temperatures required for annealing. Silicides underwent rapid at the temperatures of 300-1200 for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope(TEM) and an Auger depth profile scope were employed for the determination of vertical section structure and thickness. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates shoed low resistance up to 1000 and 800, respectively, while the conventional nickle monosilicide showed low resistance below 700. Through TEM analysis, we confirmed that a uniform, 20 -thick silicide layer formed on the single-crystal silicon substrate for the Ir-inserted case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of 1000. Auger depth profile analysis also supports the presence of thismixed microstructure. Our result implies that our newly proposed iridium-added NiSi process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.27-36
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• 2006

약 10%이하의 Pt 또는 Ir 첨가시켜 니켈모노실리싸이드를 고온에서 안정화 시키는 것이 가능한지 확인하기 위해서 활성화영역을 가정한 단결정 실리콘 웨이퍼와 게이트를 상정한 폴리 실리콘 웨이퍼 전면에 Ni, Pt, Ir을 열증착기로 성막하여 10 nm-Ni/l nm-Pt/(poly)Si, 10 nm-Ni/l nm-Ir/(poly)Si 구조를 만들었다. 준비된 시편을 쾌속 열처리기를 이용하여 40초간 실리사이드화 열처리 온도를 $300^{\circ}C{\sim}1200^{\circ}C$ 범위에서 변화시켜 두께 50nm의 실리사이드를 완성하였다. 완성된 Pt와 Ir이 첨가된 니켈실리사이드의 온도별 전기저항변화, 두께변화, 표면조도변화, 상변화, 성분변화를 각각 사점전기저항측정기와 광발산주사전자현미경, 주사탐침현미경, XRD와 Auger depth profiling으로 각각 확인하였다. Pt를 첨가한 결과 기판 종류에 관계없이 기존의 니켈실리사이드 공정에 의한 NiSi와 비교하여 $700^{\circ}C$ 이상의 NiSi 안정화 구역을 넓히는 효과는 없었고 면저항이 커지는 문제가 있었다. Ir을 삽입한 경우는 단결정 실리콘 기판에서는 $500^{\circ}C$ 이상에서의 NiSi와 동일하게 $1200^{\circ}C$까지 안정한 저저항을 보여서 Ir이 효과적으로 Ni(Ir)Si 형태로 $NiSi_{2}$로의 상변태를 적극적으로 억제하는 특성을 보이고 있었고, 다결정 기판에서는 $850^{\circ}C$까지 효과적으로 NiSi의 고온 안정성을 향상시킬 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• 한국재료학회지
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• 제13권1호
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• pp.43-47
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• 2003

As and BF$_2$dopants are implanted for the formation of source/drain with dose of 1${\times}$10$^{15}$ ions/$\textrm{cm}^2$∼5${\times}$10$^{15}$ ions/$\textrm{cm}^2$ then formed cobalt disilicide with Co/Ti deposition and doubly rapid thermal annealing. Appropriate ion implantation and cobalt salicide process are employed to meet the sub-0.13 $\mu\textrm{m}$ CMOS devices. We investigated the process results of sheet resistance, dopant redistribution, and surface-interface microstructure with a four-point probe, a secondary ion mass spectroscope(SIMS), a scanning probe microscope (SPM), and a cross sectional transmission electron microscope(TEM), respectively. Sheet resistance increased to 8%∼12% as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{V}$ , while sheet resistance uniformity showed very little variation. SIMS depth profiling revealed that the diffusion of As and B was enhanced as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{＋}$ . The surface roughness of root mean square(RMS) values measured by a SPM decreased as dose increased in $CoSi_2$$n^{＋}$ , while little variation was observed in $CoSi_2$$p^{＋}$ . Cross sectional TEM images showed that the spikes of 30 nm∼50 nm-depth were formed at the interfaces of $CoSi_2$$n^{＋}$ / and $CoSi_2$/$p^{＋}$, which indicate the possible leakage current source. Our result implied that Co/Ti cobalt salicide was compatible with high dose sub-0.13$\mu\textrm{m}$ process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.