• Korean Journal of Materials Research
• /
• v.21 no.5
• /
• pp.243-249
• /
• 2011

To reduce manufacturing costs of crystalline silicon solar cells, silicon wafers have become thinner. In relation to this, the properties of the aluminium-back surface field (Al-BSF) are considered an important factor in solar cell performance. Generally, screen-printing and a rapid thermal process (RTP) are utilized together to form the Al-BSF. This study evaluates Al-BSF formation on a (111) textured back surface compared with a (100) flat back surface with variation of ramp up rates from 18 to $89^{\circ}C$/s for the RTP annealing conditions. To make different back surface morphologies, one side texturing using a silicon nitride film and double side texturing were carried out. After aluminium screen-printing, Al-BSF formed according to the RTP annealing conditions. A metal etching process in hydrochloric acid solution was carried out to assess the quality of Al-BSF. Saturation currents were calculated by using quasi-steady-state photoconductance. The surface morphologies observed by scanning electron microscopy and a non-contacting optical profiler. Also, sheet resistances and bulk carrier concentration were measured by a 4-point probe and hall measurement system. From the results, a faster ramp up during Al-BSF formation yielded better quality than a slower ramp up process due to temperature uniformity of silicon and the aluminium surface. Also, in the Al-BSF formation process, the (111) textured back surface is significantly affected by the ramp up rates compared with the (100) flat back surface.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.08a
• /
• pp.97-97
• /
• 2013

Recently, Cu2ZnSn(S,Se)4 (CZTSS), which is one of the In- and Ga- free absorber materials, has been attracted considerable attention as a new candidate for use as an absorber material in thin film solar cells. The CZTSS-based absorber material has outstanding characteristics such as band gap energy of 1.0 eV to 1.5 eV, high absorption coefficient on the order of 104 cm-1, and high theoretical conversion efficiency of 32.2% in thin film solar cells. Despite these promising characteristics, research into CZTSS based thin film solar cells is still incomprehensive and related reports are quite few compared to those for CIGS thin film solar cells, which show high efficiency of over 20%. I will briefly overview the recent technological development of CZTSS thin film solar cells and then introduce our research results mainly related to sputter based process. CZTSS thin film solar cells are prepared by sulfurization of stacked both metallic and sulfide precursors. Sulfurization process was performed in both furnace annealing system and rapid thermal processing system using S powder as well as 5% diluted H2S gas source at various annealing temperatures ranging from $520^{\circ}C$ to $580^{\circ}C$. Structural, optical, microstructural, and electrical properties of absorber layers were characterized using XRD, SEM, TEM, UV-Vis spectroscopy, Hall-measurement, TRPL, etc. The effects of processing parameters, such as composition ratio, sulfurization pressure, and sulfurization temperature on the properties of CZTSS absorber layers will be discussed in detail. CZTSS thin film solar cell fabricated using metallic precursors shows maximum cell efficiency of 6.9% with Jsc of 25.2 mA/cm2, Voc of 469 mV, and fill factor of 59.1% and CZTS thin film solar cell using sulfide precursors shows that of 4.5% with Jsc of 19.8 mA/cm2, Voc of 492 mV, and fill factor of 46.2%. In addition, other research activities in our lab related to the formation of CZTS absorber layers using solution based processes such as electro-deposition, chemical solution deposition, nano-particle formation will be introduced briefly.

• Korean Journal of Materials Research
• /
• v.8 no.6
• /
• pp.484-492
• /
• 1998

The formation mechanism of the epitaxial cobalt silicide from Co/Ti/OOO) Si structure has been investigated. The transition temperature of CoSi to CoSi, was found to increase with increasing the Ti interlayer thickness, which may be owing to the occupation of the tetrahedral sites by Ti atoms in the CoSi crystal structure as well as the blocking effect of the Ti interlayer on the diffusion of Co. Also, the Co- Ti-O ternary compound formed at the metal! Si interface at the begining of silicidation, which seems to play an important role in epitaxial growth of Co silicide. The final layer structures obtained after a rapid thermal annealing of the Cot Ti/( 100) Si bi-layer structure turned out to be Ti oxide/Co- Ti-Si/epi-$CoSi_2$/OOO)

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.3
• /
• pp.497-504
• /
• 2019

We fabricated $HfO_2$ thin films using RF magnetron sputtering method, and investigated structural and optical properties of $HfO_2$ thin films with RTA temperatures in $N_2$ ambient. $HfO_2$ thin films exhibited polycrystalline structure regardless of annealing process, FWHM of M (-111) showed reduction trend. The surface roughness showed the smallest of 3.454 nm at a annealing temperature of $600^{\circ}C$ in result of AFM. All $HfO_2$ thin films showed the transmittance of about 80% in visible light range. By fitting the refractive index from the transmittance and reflectance to the Sellmeir dispersion relation, we can predict the refractive index of the $HfO_2$ thin film according to the wavelength. The $HfO_2$ thin film annealed at $600^{\circ}C$ exhibited a high refractive index of 2.0223 (${\lambda}=632nm$) and an excellent packing factor of 0.963.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.4
• /
• pp.202-208
• /
• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.1
• /
• pp.25-32
• /
• 2007

We investigated the silicide reaction stability between 10 nm-Col-xNix alloy films and silicon substrates with the existence of 4 nm-thick natural oxide layers. We thermally evaporated 10 nm-Col-xNix alloy films by varying $x=0.1{\sim}0.9$ on naturally oxidized single crystal and 70 nm-thick polycrystalline silicon substrates. The films structures were annealed by rapid thermal annealing (RTA) from $600^{\circ}C$ to $1100^{\circ}C$ for 40 seconds with the purpose of silicidation. After the removal of residual metallic residue with sulfuric acid, the sheet resistance, microstructure, composition, and surface roughness were investigated using a four-point probe, a field emission scanning electron microscope, a field ion bean4 an X-ray diffractometer, and an Auger electron depth profiling spectroscope, respectively, to confirm the silicide reaction. The residual stress of silicon substrate was also analyzed using a micro-Raman spectrometer We report that the silicide reaction does not occur if natural oxides are present. Metallic oxide residues may be present on a polysilicon substrate at high silicidation temperatures. Huge residual stress is possible on a single crystal silicon substrate at high temperature, and these may result in micro-pinholes. Our results imply that the natural oxide layer removal process is of importance to ensure the successful completion of the silicide process with CoNi alloy films.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.1
• /
• pp.16-22
• /
• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• Korean Journal of Materials Research
• /
• v.19 no.2
• /
• pp.90-94
• /
• 2009

The development of low-k materials is essential for modern semiconductor processes to reduce the cross-talk, signal delay and capacitance between multiple layers. The effect of the $CH_4$ concentration on the formation of SiOC(-H) films and their dielectric characteristics were investigated. SiOC(-H) thin films were deposited on Si(100)/$SiO_2$/Ti/Pt substrates by plasma-enhanced chemical vapor deposition (PECVD) with $SiH_4$, $CO_2$ and $CH_4$ gas mixtures. After the deposition, the SiOC(-H) thin films were annealed in an Ar atmosphere using rapid thermal annealing (RTA) for 30min. The electrical properties of the SiOC(-H) films were then measured using an impedance analyzer. The dielectric constant decreased as the $CH_4$ concentration of low-k SiOC(-H) thin film increased. The decrease in the dielectric constant was explained in terms of the decrease of the ionic polarization due to the increase of the relative carbon content. The spectrum via Fourier transform infrared (FT-IR) spectroscopy showed a variety of bonding configurations, including Si-O-Si, H-Si-O, Si-$(CH_3)_2$, Si-$CH_3$ and $CH_x$ in the absorbance mode over the range from 650 to $4000\;cm^{-1}$. The results showed that dielectric properties with different $CH_4$ concentrations are closely related to the (Si-$CH_3$)/[(Si-$CH_3$)+(Si-O)] ratio.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.45-49
• /
• 2014

In this study, we grew non-polar ZnO nanostructure on (1-102) R-plane sapphire substrates. As for growth method of ZnO, we used hydrothermal synthesis which is known to have the advantages of low cost and easy process. For growth of non-polar, the deposited AZO seed buffer layer with of 80 nm on R-plane sapphire by radio frequency magnetron sputter was annealed by RTA(rapid thermal annealing) in the argon atmosphere. After that, we grew ZnO nanostructure on AZO seed layer by the added hexamethylenetramine (HMT) solution and sodium citrate at $90^{\circ}C$. With two types of additives into solution, we investigated the structures and shapes of ZnO nanorods. Also, we investigate the possibility of formation of 2D non-polar ZnO layer by changing the ratio of two additives. As a result, we could get the non-polar A-plane ZnO layer with well optimized additives' concentrations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.350-353
• /
• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.