• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.2
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• pp.128-132
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• 1998

2/65/35 PLZT stock solution prepared by Sol-Gel processing was spin-coated on ITO coated glass and annealed by RTA(Rapid Thermal Annealing). The crystal structure of films was reported based on the observation of crystallization process and microstructure of the film fabricated at different fabrication condition. Films were crystallized into rhombohedral structure by annealing at $750^{\circ}C$ for 5 min. As the annealing temperature increased, the size of rosette structure of the films was grown up from $2.4{\mu}m$ to $15{\mu}m$, dielectric constant was increased, coercive field was decreased 33.82 kV/cm, remnant polarization was increased to 39.84 ${\mu}C/cm^2$ and Optical transmittance was decreased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.54-58
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• 1994

H$_2$ bake and GeH$_4$ clean are used as a in-situ pre-clean method in low temperature Si based epitaxial growth technology using rapid thermal processing chemical vapor deposition (RTPCVD). In this paper, the H$_2$ bake and GeH$_4$ clean processes are optimized for low surface defect density using Taguchi method. In H$_2$ bake process, the epitaxial growth temperature affects dominantly on the surface defect density, and the next affecting factors are H$_2$ bake temperature and rinse time in de-ionised water. In GeH$_4$ clean process, GeH$_4$ clean temperature affects most strongly on the surface defect density, and the minor factor is GeH$_4$flow rate. The optimum process conditions predicted fly Taguchi method agree well with tile experimental data in both in-situ clean processes.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.328-331
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• 1988

Sealed Interface Local Oxidation (SILO) technology has been investigated using a nitride/oxide/nitride three-layered sandwich structure. P-type silicon substrate was either nitrided by rapid thermal processing, or silicon nitride was deposited by LPCVD method. A three-layered sandwich structure was patterned either by reactive ion etch (RIE) mode or by plasma mode. Sacrificial oxidation conditions were also varied. Physical characterization such as cross-section analysis of field oxide, and electrical characterization such as gate oxide integrity, junction leakage and transistor behavior were carried out. It was found that bird's beak was nearly zero or below 0.1um, and the junction leakages in plasma mode were low compared to devices of the same geometry patterned in RIE mode, and gate oxide integrity and transistor behavior were comparable. Conclusively, SILO process is compatible with conventional local oxidation process.

• The Korean Journal of Ceramics
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• v.6 no.3
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• pp.245-249
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• 2000

Consolidation of amorphous powders is emerging as a route for synthesis of high strength composite materials. Diffusion processes necessary for consolidation are expected to be more rapid in amorphous state(SRO) than in the crystalline state(LRO). A new synthesis technique of exploiting polymeric ceramic precursors(polysilazane and polyborosilazane) is derived for Si$_3$N$_4$/SiC and boron-modified nanocomposites for extremely high temperature applications up to 200$0^{\circ}C$. The characterization methods include thermal analysis of DTA, and XRD, NMR, TEM, after pyrolysis, as a function of time and temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.105-112
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• 1993

Oxide and reoxidized-nitrided-oxide were formed by furnace oxidation and rapid thermal processing (RTP). MOS capacitor and n-MOSFET's with those films as gate insulators were fabricated. The electrical characteristics of insulators were evaluated by current-voltage, high-frequency capacitance-voltage (C-V), and time-dependent dielectrical breakdown (TDDB) measurements. The hot carrier effects of MOSFET's were also investigated. Time-dependent dielectrical breakdown (TDDB) characteristics show that the life time of reoxidized-nitrided-oxide films is about 3 times longer than that of oxides. Hot carrier effects reveal that the life time of MOSFET's with reoxidized-nitrided-oxides is about 3 times longer than that of MOSFET's with oxides. Therefore, it is found that the reliability of dielectric films estimated by the hot carrier effects of MOSFET's is consistent with that of dielectric films from TDDB method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.53-60
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• 2009

$ZrTiO_4$ dielectric thin films were coated by metal-organic decomposition, and annealed by rapid thermal processing up to $900^{\circ}C$ for their crytallization. Crystallized single-phase $ZrTiO_4$ thin films were fabricated above the annealing temperature of $800^{\circ}C$, but their grains were randomly oriented without specific textured orientation. Best dielectric properties were presented by the sample annealed at $800^{\circ}C$ which had crystalline structure and flat surface. Dielectric constant of the film was maintained at 32 throughout full frequency range up to 6 GHz, and dielectric loss was varied between 0.01 and 0.04.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2548-2550
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• 2000

RTP(Rapid Thermal Processing)은 IC제조 공정과 관련된 열처리 과정에 사용되는 단일 웨이퍼프로세스 기술이다. 반도체 웨이퍼를 고속 열처리할 때 웨이퍼별로 작은 반응실에서 가열, 가공, 냉각된다. 현재 사용되는 반도체 열처리장비는 고온로(furnace)에의해 대부분 이루어지지만, 시간이 많이 걸려서 주문형반도체 생산과 같은 다양한 종류의 웨이퍼를 소량 생산하는데는 부적절하다. 이에 매우 적은 시간이 소요되는 RTP장비가 많이 연구되고 있다. 그러나 RTP는 예기치 못한 몇 가지의 문제점을 일으킨다. 그중 하나는 웨이퍼 표면에 분포된 온도의 불 균일성이다. 이러한 불 균일성은 웨이퍼의 표면에 심각한 왜곡(distortion)을 일으켜 좋지 못한 결과를 가져오게 한다. 이번 논문의 목적은 RTP시스템을 수학적으로 모델링하고, 이를 이용하여 멀티 램프 시스템의 입력값을 조절하여 이미 배치된 램프에 대한 최적의 온도 균일도에 알맞은 각 램프입력을 구하여 램프 입력 프로파일을 만들고 또한 이를 이용하여 외란에 대한 PID 제어기 설계를 목표로 한다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.3
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• pp.424-430
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• 1996

The present processing sequence for solar cells is very elaborate and ads to the cost of the fabricated cells. This processing cost, which accounts for about 30% of the total cost, can be reduced if the many high temperature sequences can be reduced without significantly reducing the cells energy conversion efficiency. By using the spin-on glasses (SOG) in conjunction with the conventional tube furnace (CTF) or rapid thermal annealer (RTA), the many high temperature process can be reduced to only one. In order to achieve efficiencies similar to the standard high temperature sequences using the solid or liquid sources, some basic characterization of the groove diffusion is necessary to ascertain the its suitability. This paper describes the work done in diffusing the buried contact grooves using the phosphorus SOG.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.93-96
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• 2002

In this study, PZT thin films were fabricated using sol-gel processing onto Si/$SiO_2$/Ti/Pt substrates. PZT sol with different Zr/Ti ratio(20/80, 30/70, 40/60, 52/48) were prepared, respectively. The films were fabricated by using the spin-coating method on substrates. The films were heat treated at $450^{\circ}C$, $650^{\circ}C$ by rapid thermal annealing(RTA). The preferred orientation of the PZT thin films were observed by X-ray diffraction(XRD), and Scanning electron microscopy(SEM). All of the resulting PZT thin films were crystallized with perovskite phase. The fine crystallinity of the films were fabricated. Also, we found that the ferroelectric properties from the dielectric constant of the PZT thin films were over 600 degrees, P-E hysteresis constant. And the leakage current densities of films were lower than $10^{-8}A/cm^2$. It is concluded that the PZT thin films by sol-gel process to be convinced of application for ferroelectric memory device.

• Elastomers and Composites
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• v.58 no.1
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• pp.44-56
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• 2023

Additive manufacturing (AM) or three-dimensional (3D) printing of metals has been drawing significant attention due to its reliability, usefulness, and low cost with rapid prototyping. Among the various AM technologies, fused deposition modeling (FDM) or fused filament fabrication is receiving much interest because of its simple manufacturing processing, low material waste, and cost-effective equipment. FDM technology uses metal-filled polymer filaments for 3D printing, followed by debinding and sintering to fabricate complex metal parts. An efficient binder is essential for producing polymer filaments and the thermal post-processing of printed objects. This study involved an in-depth investigation of and a fabrication route for a novel multi-component binder system with steel alloy powder (45 vol.%) ranging from filament fabrication and 3D printing to debinding and sintering. The binder system consisted of polyvinyl pyrrolidone (PVP) as a binder and thermoplastic polyurethane (TPU) and polylactic acid (PLA) as a carrier. The PVP binder held the metal components tightly by maintaining their stoichiometry, and the TPU and PLA in the ratio of 9:1 provided flexibility, stiffness, and strength to the filament for 3D printing. The efficacy of the binder system was examined by fabricating 3D-printed cubic structures. The results revealed that the thermal debinding and sintering processes effectively removed the binder/carrier from the cubic structures, resulting in isotropic shrinkage of approximately 15.8% in all directions. The scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX) patterns displayed the microstructure behavior, phase transition, and elemental composition of the 3D cubic structure.