• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.201-206
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• 2002

Pd/Si/Pd/Ti/Au ohmic contact to n-type InGaAs was investigated with rapid thermal annealing conditions. Minimum specific contact resistivity of $3.9\times10^{-7}\Omega\textrm{cm}^2$ was achieved at $400^{\circ}C$/20sec. This was related to the formation of Pd-Si compounds by rapid thermal annealing and the in-diffusion of Si atoms to InGaAs surface. However, the specific contact resistivity increased slightly to low-$10^{-6}\Omega \textrm{cm}^2$ at $400^{\circ}C$ for longer than 30 seconds, and to high-$10^{-7}$ at 425~$450^{\circ}C$ for 10 seconds. This resulted from the formation of Pd-Ga compounds. Superior ohmic contact and non-spiking planar interface between ohmic materials and InGaAs were maintained after annealing at high temperature. Therefore, this thermally stable ohmic contact system is a promising candidate for compound semiconductor devices.

• Journal of the Korean Vacuum Society
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• v.10 no.2
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• pp.219-224
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• 2001

Pd/Ge/Ti/Pt ohmic contact to n-type InCaAs was investigated. Minimum specific contact resistivity of $3.7\times10^{-6}\; \Omega\textrm{cm}^2$ was achieved by rapid thermal annealing at $400^{\circ}C$ for 10 seconds. This was related to the formation of Pd-Ge compounds and the in-diffusion of Ge atoms to InGaAs surface. However, the specific contact resistivity increased slightly to $low-10^5\; \Omega\textrm{cm}^2$ in the case of longer annealing time. Superior ohmic contact and non-spiking planar interface between ohmic materials and InGaAs were maintained after annealing at high temperature. Therefore, this thermally stable ohmic contact system is a promising candidate for compound semiconductor devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.513-519
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• 2001

We proposed Si-rich tungsten silicide (WSix) films for alternate gate electrode of deep-submicron MOSFETs. The investigation of WSix films deposited directly on SiO$_2$ indicated that the annealing of as-deposited films using a rapid thermal processor (RTP) results in low resitivity, as well as negligible fluorine (F) diffusion. Specifically, the resitivity of RTP-annealed samples at 800 $^{\circ}C$ for 3 minutes in vacuum was ~160 $\mu$$\Omega$ . cm, and the irregular growth of an extra SiO$_2$ layer due to F diffusion during annealing has not been observed. In addition, the analysis of the WSix-SiO$_2$-Si (MOS) capacitors exhibits excellent electrical characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.771-780
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• 2001

It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.

• Korean Journal of Materials Research
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• v.13 no.1
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• pp.43-47
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• 2003

As and BF$_2$dopants are implanted for the formation of source/drain with dose of 1${\times}$10$^{15}$ ions/$\textrm{cm}^2$∼5${\times}$10$^{15}$ ions/$\textrm{cm}^2$ then formed cobalt disilicide with Co/Ti deposition and doubly rapid thermal annealing. Appropriate ion implantation and cobalt salicide process are employed to meet the sub-0.13 $\mu\textrm{m}$ CMOS devices. We investigated the process results of sheet resistance, dopant redistribution, and surface-interface microstructure with a four-point probe, a secondary ion mass spectroscope(SIMS), a scanning probe microscope (SPM), and a cross sectional transmission electron microscope(TEM), respectively. Sheet resistance increased to 8%∼12% as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{V}$ , while sheet resistance uniformity showed very little variation. SIMS depth profiling revealed that the diffusion of As and B was enhanced as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{＋}$ . The surface roughness of root mean square(RMS) values measured by a SPM decreased as dose increased in $CoSi_2$$n^{＋}$ , while little variation was observed in $CoSi_2$$p^{＋}$ . Cross sectional TEM images showed that the spikes of 30 nm∼50 nm-depth were formed at the interfaces of $CoSi_2$$n^{＋}$ / and $CoSi_2$/$p^{＋}$, which indicate the possible leakage current source. Our result implied that Co/Ti cobalt salicide was compatible with high dose sub-0.13$\mu\textrm{m}$ process.

• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.120-125
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• 2010

For the fabrication of PMOS and integrated semiconductor devices, B, $BF_2$ and dual elements with B and $BF_2$ can be implanted in silicon. 15 keV B ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{16}\;cm^{-2}$. 67 keV $BF_2$ ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{15}\;cm^{-2}$. For dual implantations, 67 keV $BF_2$ and 15keV B were carried out with two implantations with dose of $1.5{\times}10^{15}\;cm^{-2}$ instead of $3.0{\times}10^{15}\;cm^{-2}$, respectively. For the electrical activation, the implanted samples were annealed with rapid thermal annealing at $1,050^{\circ}C$ for 30 seconds. The implanted profiles were characterized by using secondary ion mass spectrometry in order to measure profiles. The implanted and annealed results show that concentration profiles for the ${BF_2}^+$ implant are shallower than those for a single $B^+$ and dual ($B^+$ and ${BF_2}^+$) implants in silicon. This effect was caused by the presence of fluorine which traps interstitial silicon and ${BF_2}^+$ implants have lower diffusion effect than a single and dual implantation cases. For the fabricated diodes, current-voltage (I-V) and capacitance-voltage (C-V) were also measured with HP curve tracer and C-V plotter. Electrical measurements showed that the dual implant had the best result in comparison with the other two cases for the turn on voltage characteristics.