• Korean Journal of Optics and Photonics
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• v.22 no.2
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• pp.83-89
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• 2011

In order to improve the calculation speed of an integrating-sphere simulator based on a ray-tracing method, parallel processing with OpenMP directive was implemented into the simulator and the randomness of Monte Carlo method was guaranteed by utilizing a parallel random number generator. It was confirmed that simulation results obtained with more than $10^7$ rays showed good agreement with theoretical results within the error range of 0.5%, and that the calculation speed improved as the number of threads increased. Finally, the spatial response distribution functions of a real integrating sphere were simulated and compared with previous results.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1759-1769
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• 1997

The Error BackPropagation (EBP) algorithm for multi-layered neural networks is widely used in various areas such as associative memory, speech recognition, pattern recognition and robotics, etc. Nevertheless, many researchers have continuously published papers about improvements over the original EBP algorithm. The main reason for this research activity is that EBP is exceeding slow when the number of neurons and the size of training set is large. In this study, we developed new learning speed acceleration methods using variable learning rate, variable momentum rate and variable slope for the sigmoid function. During the learning process, these parameters should be adjusted continuously according to the total error of network, and it has been shown that these methods significantly reduced learning time over the original EBP. In order to show the efficiency of the proposed methods, first we have used binary data which are made by random number generator and showed the vast improvements in terms of epoch. Also, we have applied our methods to the binary-valued Monk's data, 4, 5, 6, 7-bit parity checker and real-valued Iris data which are famous benchmark training sets for machine learning.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1075-1082
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• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.141-150
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• 2007

This paper proposes new Steganographic model for VoIP that has very effective method using low bit encoding. Most of Steganographic models using Low bit Encoding have two disadvantages; one is that the existence of hidden secret message can be easily detected by auditory, the other is that the capacity of stego data is low. To solve these problems, this method embed more than one bit in inaudible range, so this method can improve the capacity of the hidden message in cover data. The embedding bit position is determined by using a pseudo random number generator which has seed with remaining message length, so it is hard to detect the stego data produced by the proposed method. This proposed model is able to use not only to communicate wave file with hidden message in VoIP environment but also to hide vary information which is user basic information, authentication system, etc.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.1
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• pp.49-67
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• 2016

SP 800-90B of NIST(USA) and AIS.31 of BSI(Germany) are representative statistical tests for TRNGs. In this paper, we concentrate on AIS.31 which is under the ongoing international standardization process. We examine the probabilistic meaning of each statistic of the test in AIS.31 and investigate its probability distribution. By changing significance level and the length of sample bits, we obtain formalized accept region of the test. Furthermore we propose the accept regions for some iterative tests, that are not mentioned in AIS.31, and provide some simulations.

• Journal of the Korea Computer Industry Society
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• v.3 no.12
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• pp.1679-1690
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• 2002

This paper, describe about a generation of a syllable restoration regulation for a post processing of a speech recognition and a decrease of a restoration candidate. It created a syllable restoration regulation to create a restoration candidate pronounced with phonetic value recognized through a post processing of the formula system that was a tone to recognize syllable unit phonetic value for a performance enhancement of a dialogue serial speech recognition. Also, I presented a plan to remove a regulation to create unused notation from a real life in a restoration regulation with a plan to reduce number candidate of a restoration meeting. A design implemented a restoration candidate set generator in order a syllable restoration regulation display that it created a proper restoration candidate set. The proper notation meeting that as a result of having proved about a standard pronunciation example and a word extracted from a pronunciation dictionary at random, the notation that an utterance was former was included in proved with what a generation became.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.867-875
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• 2014

Rapid development of internet service is enabling internet banking services in anywhere and anytime. However, service access through internet can be exposed to adversary easily. To prevent, current service providers execute authentication process with user's identification and password. However, majority of users use short and simple password and do not periodically change their password. As a result of this, user's password could be exposed to attacker's brute force attack. In this paper, we presented enhanced password system which guarantee higher security even though users do not change their current password. The method uses additional secret information to replace real password periodically without replacement of real password.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.5
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• pp.771-780
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• 2020

QKD(Quantum Key Distribution) is one of the protocols that can make two distant parties safely share secure keys against the threat of quantum computer. Generally, cryptographic applications which are connected to the QKD device have fixed roles as a transmitter and a receiver due to the race condition and complexity of implementation. Because the conventional QKD system is mainly applied to the link encryptor, there are no problems even if the roles of the cryptographic devices are fixed. We propose a new scheme of QKD system and protocol that is easy to extend to the QKD network by eliminating quantum key dependency between cryptographic device and QKD node. The secure keys which are generated by the TRNG(True Random Number Generator) are provided to the cryptographic applications instead of quantum keys. We design an architecture to transmit safely the secure keys using the inbound and outbound quantum keys which are shared between two nodes. In this scheme, since the dependency of shared quantum keys between two QKD nodes is eliminated, all cryptographic applicatons can be a master or a slave depending on who initiates the cryptographic communications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.