• Journal of IKEEE
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• v.27 no.4
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• pp.573-578
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• 2023

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops (DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based Digital Controlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this method effectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes are used, and upon completion of locking, the system transitions to thermometer codes, achieving high frequency linearity and reduced jitter characteristics. This approach significantly reduces the number of switches required and minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to the traditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a level equivalent to that of the thermometer-only approach. The efficacy of this technique has been validated through modeling and design at the RTL level using SystemVerilog and Verilog HDL.

• Proceedings of the Korea Contents Association Conference
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• 2011.05a
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• pp.555-556
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• 2011

액티브 RFID를 기반으로 실시간 위치정보 서비스를 구현하는 모델인 RTLS는 보안, 의료, 건설, 항공, 항만, 운송, 국방, 교통, 레저 등 실시간 위치정보가 필요한 분야에 효과적으로 활용되고 있다. 이 논문에서는 RTLS 응용 시스템을 위한 지능형 위치정보 관리시스템을 제안한다. 제안 시스템은 일반적인 데이터 관리의 기능 이외에도 상황인식 시스템에서 사용되는 규칙기반 미들웨어 Jess(Java expert system shell)를 활용하는 구조를 가진다. 규칙을 이용한 추론 기능을 도입함으로써 응용 시스템의 정확성을 높일 수 있는 특징을 가진다.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.167-170
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• 2003

In this paper, a design and experiment of PCI Express Core verification Model is described. The model targeting Endpoint core verification is designed by using newly-emerging SystemC which is a system design language based on a new C++ class library and simulation engine. In the verification model, we developed a SystemC Host System model which act as a Root Complex and Device Driver dedicated to the PCI Express Endpoint RTL Core. The test of Host System Model is guided by scenarios which implements and acts point of Device Driver and Root Complex and shows the result of simulation. Also, We present the full structure of verification model and Host model.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2433-2438
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• 2011

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

• The Journal of the Korea Contents Association
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• v.7 no.9
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• pp.81-88
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• 2007

Having been speed development of information delivery using the mobile phone, it is generalization. The Mobile has one of the importance for their information searcher as tool. It is widely recognized that tourism information can be defined as useful and reliable reference which significantly influence the traveler' decision-making. This paper presents pioneer and ongoing study of the method for the pinpionting mobile tourism information system with RTLS, 2D Barcode and mobile phone itself. And, this paper relief that benefit and influence of TCO a view on the business administration points.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1736-1739
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• 2002

The advanced in semiconductor, hardware, and software technologies enables the integration of more com- plex systems and the increasing design complexity. As system design complexity becomes more complicated, System-level design based on the If block and processor model is more needed in most of the RTL level or low level. In this paper, we present a novel approach fur the system-level design, which satisfies the various required constraints and an optimization method of image encoder based on codesign of function, algorithm, and architecture. In addition, we show an MPEG-4 encoder as a design case study. The best tradeoffs between algorithm and architecture are necessary to deliver the design with satisfying performance and area constraints. The evaluations provide the effective optimization of motion estimation, which is in charge of an amount of performance in the MPEG-4 encoder module.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.381-385
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• 2010

An aging Society solitary life old mans are increasing. The nurses have to visit old mans and must confirm their disease, because they do not act well. It is very difficult to take care old man, because the number of Nurses are small. This problem is solved by collection of data about condition of old mans from long distance. Data communication with Ethernet have benefit to collection of measurement of old man's condition. The Data storage system an long distance place are storaged data and after several day data was transmitted to the DB over the Ethernet. For Miniaturization of such system the system must be OS-less Embedded Ethernet Server system. Such system manages the file management system only with H/W. The Storage device is used SD-card. SD Card is small size and operates with small power. By using 512MB sd memory card, it is possible to storage during 5~6 years, 10 byte of temperature value per second. In this paper, we make a Embedded Ethernet Server using W3100A, Atmega128 MCU and data stroage device using SD-Card. This system operates with O/S-less Embedded Ethernet Server. We talk about file System, Storage and Ethernet. We explained about MCU Atmega128, Interface between LAN LSIand W3100A, Interface between W3100A and Phyceiver RTL8201, data I/O between MCU and SD-Card and File System. We shows the experiment device and result of monitoring.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.184-187
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• 2000

A network is an important portion of communications in these days. Because of many inconveniences of a wired-network, wireless solutions have been studied for many years. One of the results of those efforts is IEEE 802.11, wireless LAN. This paper briefly summarizes wireless LAN and specially focuses on the design of a network processor for the wireless LAN system. The processor has 16-bit instruction set suitably selected for network processing and low-power consumption. It is implemented and verified with a wireless LAN system model. The wireless LAN system is modeled in RTL excluding the RF module. The processor can be used in many wireless systems as a controller and utilized as a test module for the research of low-power schemes.