• Proceedings of the Korea Contents Association Conference
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• 2010.05a
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• pp.366-370
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• 2010

로봇 기술이 발달하면서 사람의 지령에 의해 수동적, 반복적인 작업을 수행하던 기존 전통적 로봇에서 벗어나, 스스로 외부환경을 인식하고, 상황을 판단하여 자율적으로 동작하는 지능형 로봇이 등장하였다. 이러한 로봇의 S/W개발은 편의성을 위해 범용 운영체제를 사용하여 개발하는 추세이다. 지능형 서비스의 QoS(Quality of Service)를 위해서는 로봇 미들웨어에 실시간성을 지원해야 하지만 범용 운영체제는 실시간성을 지원하지 않는 문제점이 있다. 본 논문에서는 범용 운영체제인 오픈솔라리스에 실시간성을 위한 논리적 정확성 및 시간 결정성을 보장하기 위하여 실시간 스케쥴러를 포함한 실시간 프레임 워크 RTL(Real-Time Layer)을 설계 및 구현한 내용을 기술한다. 또한 성능측정을 위해 쓰레드의 응답시간을 측정하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.30-32
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• 2000

본 논문에서는 RTL 회로의 데이터패스에 대한 테스트 용이도 분석방식과 테스트 용이화 설계방식을 제안한다. 데이터패스에 대한 테스트 용이도 분석은 콘트롤러에 대한 정보없이 RTL 회로의 데이터패스만으로 수행한다. 본 논문에서 제안한 테스팅을 고려한 설계방식은 내장된 자체 테스트(BIST)나 주사(scan)방식이 아니며, 주사 방식을 적용했을 때에 비해 본 논문에서 제안한 테스트 용이화 설계방식을 적용했을 때에 보다 적은 면적 증가율(area overhead)을 보인다는 것을 실험을 통해 확인하였다. 또한, 회로 합성 후 ATPG를 통해 적은 면적 증가만으로 높은 고장 검출율(fault coverage)을 얻을 수 있음을 보인다.

• Proceedings of the IEEK Conference
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• summer
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• pp.285-288
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• 2004

In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.11-19
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• 2010

Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.

• Journal of Korea Spatial Information System Society
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• v.10 no.4
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• pp.47-58
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• 2008

With the recent development of the ubiquitous computing technology, there are increasing interest and research in technologies such as sensors and RFID related to information recognition and location positioning in various ubiquitous fields. Especially, a standard specification was required for compatibility and interoperability in various RTLS(Real-Time Locating Systems) according to the development of RTLS to provide location and status information of moving objects using the RFID Tag. For these reasons, the ISO/IEC published the RTLS standard specification for compatibility and interoperability in RTLS. Therefore, in this paper, we designed and im plemented RTLS based on the spatial DSMS(Data Stream Management Stream) for efficiently managing and searching the incoming data stream of moving objects. The spatial DSMS is an extended system of STREAM(STanford stREam datA Manager) developed by Standford University to make various spatial operations possible. RTLS based on the spatial DSMS uses the SOAP(Simple Object Access Protocol) message between client and server for interoperability and translates client's SOAP message into CQL(Continuous Query Language) of the spatial DSMS. Finally, we proved the efficiency of RTLS based on the spatial DSMS by applying it for the staff location management service.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.932-935
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• 2008

유비쿼터스 환경에서 '상황인식 서비스(context-aware service)'를 구현하기 위해서는 위치 정보 및 이를 기반으로 한 주변의 상황에 대한 정보, 그리고 거기에 적합한 서비스 제공 인프라를 구축하는 것이 필요하다. 본 연구에서는 최근 IEEE 802.15.4/a에서 표준화가 완료된 CSS(Chirp Spread Spectrum) 기반의 RTLS를 구축하고 성능을 평가한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.